Two new arithmetic operations

Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate(MAC) and inner product are among some of the frequently used computation Intensive Arithmetic Functions(CIAF) currently implemented in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT), filtering and in microprocessors m its arithmetic and logic unit. Since multiplication dominates the execution tune of most DSP algorithms, so there is a need of high speed multiplier. Currently, multiplication time is still the dominant factor in determining the instruction cycle time of a DSP chip. The demand for high speed processing has been increasing as a result of expanding computer and signal processing applications. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications . One of the key arithmetic operations in such applications is multiplication and the development of fast multiplier circuit has been a subject of interest over decades. Multiplier based on Vedic Mathematics is one of the fast and low power multiplier. Employing this technique in the computation algorithms will reduce the complexity, execution time, power etc. This vedic based multiplier is compared with binary multiplier(partial products method).

The purpose of this paper is to summarize proposed specifications for floating-point arithmetic and elementary functions. The topics considered are: the base of the number system, precision control, number representation, arithmetic operations, mother basic operations, elementary functions, and exception handling. The possibility of doing without fixed-point arithmetic is also discussed. The specifications are intended to be entirely at the level of a programming language such as Fortran. The emphasis is on convenience and simplicity from the user's point of view. The specifications are not complete every detail, but it is intended that they be complete in spirit — some further details, especially syntatic details, would have to be provided, but the proposals are otherwise relatively complete.

This paper describes an approach to the use of genetic programming (GP) for the automatic detection of rhythmic stress in spoken New Zealand English. A linear-structured GP system uses speaker independent prosodic features and vowel quality features as terminals to classify each vowel segment as stressed or unstressed. Error rate is used as the fitness function. In addition to the standard four arithmetic operators, this approach also uses several other arithmetic, trigonometric, and conditional functions in the function set. The approach is evaluated on 60 female adult utterances with 703 vowels and a maximum accuracy of 92.61% is achieved. The approach is compared with decision trees (DT) and support vector machines (SVM). The results suggest that, on our data set, GP outperforms DT and SVM for stress detection, and GP has stronger automatic feature selection capability than DT and SVM.KeywordsSupport Vector MachineProsodic FeatureLexical StressVowel QualityGenetic Programming SystemThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

An application of an evolutionary approach to hardware design is presented. A genetic algorithm was developed to discover good designs for quantum computer algorithms. The algorithms are expressed as quantum operator sequences applied in a circuit model. The circuits discovered are configurations of special purpose quantum computers. We have been exploring the evolution of algorithms as alternative configurations of hardware. By simulation it is established that the circuits will correctly compute a small collection of basic, low-level functions. Experiments produced designs for primitive quantum computers that evaluate logical or arithmetic functions with a total of twelve or fewer inputs and outputs.

We study adding aggregate operators, such as summing up elements of a column of a relation, to logics with counting mechanisms. The primary motivation comes from database applications, where aggregate operators are present in all real life query languages. Unlike other features of query languages, aggregates are not adequately captured by the existing logical formalisms. Consequently, all previous approaches to analyzing the expressive power of aggregation were only capable of producing partial results, depending on the allowed class of aggregate and arithmetic operations. We consider a powerful counting logic, and extend it with the set of all aggregate operators. We show that the resulting logic satisfies analogs of Hanf's and Gaifman's theorems, meaning that it can only express local properties. We consider a database query language that expresses all the standard aggregates found in commercial query languages, and show how it can be translated into the aggregate logic, thereby providing a number of expressivity bounds, that do not depend on a particular class of arithmetic functions, and that subsume all those previously known. We consider a restricted aggregate logic that gives us a tighter capture of database languages, end also use it to show that some questions on expressivity of aggregation cannot be answered without resolving some deep problems in complexity theory.

Embedded systems used in real-time applications require low power, less area and high computation speed. For digital signal processing, image processing and communication applications, data are often received at a continuously high rate. The type of necessary arithmetic functions and matrix operations may vary greatly among different applications. The RTL-based design and verification of one or more of these functions could be time-consuming. Some High Level Synthesis tools reduce this design and verification time but may not be optimal or suitable for low power applications. The design tool proposed in this paper can improve the design time and reduce the verification process. The design tool offers a fast design and verification platform for important matrix operations. These operations range from simple addition to more complex matrix operations such as LU and QR factorizations. The proposed platform can improve design time by reducing verification cycle. This tool generates Verilog code and its testbench that can be realized in FPGA and VLSI systems. The designed system uses MATLAB-based verification and reporting.

Intensive Mathematics I (MAT037) is a basic mathematics course that is offered for pre-diploma students at Universiti Teknologi MARA (UiTM). The pre-diploma programme is a UiTM initiative that offers a special path for students who have completed the Sijil Pelajaran Malaysia (SPM) but do not meet the minimal requirements to further their studies at public universities. These students will be given the opportunity to apply to study at the diploma level in any of the UiTM faculties of their choice through the pre-diploma programme. MAT037 is designed to enhance the fundamentals of mathematics to prepare students for the diploma courses. This course content includes arithmetic operations, algebra, polynomials, equations, functions, indices, and logarithms. It also covers sequence, business mathematics, statistics, and applications of mathematics in basic business, finance, and investments. Based on the results of MAT037 for the past five semesters, the statistics showed that there were always a number of students who failed to perform. Therefore, this study aims to find out whether students’ involvement in the learning process (actively or passively) correlates with their mathematics (MAT037) performance. Pre-diploma students at the UiTM Sarawak Branch, Mukah campus were the target population. A total of 175 students took part in this study. This research adopted the quantitative approach, and the correlational and quasi-experimental research designs were employed in this study. The questionnaire survey method was a measuring instrument for data collection. The data collected was analyzed using the IBM Statistical Package for Social Sciences (SPSS). The results indicated that the correlation was statistically significant and that there was a moderate positive correlation between students’ involvement in the learning process and their MAT037 performance.

Optical fiber has been widely used in telecommunication networks due to its inherent advantages of considerable bandwidth and ultrahigh-speed light transmission. However, it only serves as the transmission medium and cannot identify and process data directly in the fiber. One solution is to simulate neuromorphic functions directly in fibers. Here, Ge2Sb2Te5-assisted all-fiber synapses are proposed for information recognition and processing. The synaptic spike-timing-dependent plasticity, an important synaptic learning rule in Hebbian theory, can be mimicked by controlling the taper extension of the tapered fiber and integrating Ge2Sb2Te5 on its waist. The designed all-fiber synapse interacts efficiently with Ge2Sb2Te5 to alter light transmission, expressed as the synaptic weight. This synapse exhibits 10-level weight, 22% transmission contrast ratio, and 180 ns fast switching time for a single pulse. Additionally, the character recognition and arithmetic operation functions are demonstrated based on the proposed all-fiber synapses, inspiring a new paradigm for in-fiber processing.

The building blocks of several block ciphers involve arithmetic operations, bitwise operations and non-linear functions given as SBoxes. In the context of implementations secure against Side Channel Analysis, these operations shall not leak information on secret data. To this end, masking is a widely used protection technique. Propagating the masks through non-linear functions is a necessary task to achieve a sound and secure masked implementation. This paper describes an efficient method to securely access N SBoxes when the N inputs are encoded as a single word arithmetically masked. This problematic arises for instance in a secure implementation of the standard block ciphers GOST or SEED. A method using state of the art algorithms would be to first perform an arithmetic to boolean mask conversion before independently accessing the N SBoxes. Compared to this method, the algorithm proposed in this paper needs less code, less random generation and no extra memory. This makes our algorithm particularly suitable for very constrained devices. As a proof of concept, we compare an implementation in 8051 assembly language of our algorithm to the existing solutions.

D. Dubois and H. Prade (1981) introduced the concept of weakly noninteractive fuzzy numbers whose operations are based on the extension principle corresponding to each t-norm in place of the minimum operator. Some properties of weakly noninteractive fuzzy numbers and their practical method of calculation are investigated. Three parameters indicating the mean value and the left/right spreads of the fuzzy number are considered. Various parameter formulas for arithmetic operations and power function operation of certain kinds of weakly noninteractive fuzzy numbers involving no-interactive fuzzy numbers are presented. The formulas are applicable to both cases of the L-R fuzzy number of Dubois and Prade (1978) and an improved version of the calculation method using the digital representation. An attempt is made to classify general t-norms into the three classes from the viewpoint of the parameter formulas. The results of numerical experiments are shown for the formulas and the calculation method using the digital representation. >

A novel arithmetic operation function utilizing height of interval type-2 fuzzy sets to express risk preference: case study of remotely controlled autonomous ship

Probabilistic arithmetic. I. Numerical methods for calculating convolutions and dependency bounds

Parallel processors with bit-serial processing elements (PE's) usually implement arithmetic functions by a sequence of word-level arithmetic operations; however, basic operations must be specified at the bit level. In this correspondence the possibility of more efficiently implementing a function with a special tailored sequence of bit-serial operations is considered. A general scheme is described for generating efficient programs to implement arbitrary functions on bit-serial-arithmetic processors. This scheme is based on logic design methodology and involves designing a logic network to realize a desired function. The parallel processor is then used to efficiently simulate a set of these networks. Heuristic design algorithms are used to generate the logic networks; several algorithms are described and compared with some benchmark functions. Several efficient PE designs are described and analyzed.

Living systems use enzymatic reaction networks to process biochemical information and make decisions in response to external or internal stimuli. Herein, we present a modular and reusable platform for molecular information processing using enzymes immobilised in hydrogel beads and compartmentalised in a continuous stirred tank reactor. We demonstrate how this setup allows us to perform simple arithmetic operations, such as addition, subtraction and multiplication, using various concentrations of substrates or inhibitors as inputs and the production of a fluorescent molecule as the readout.

Algorithms for the high speed binary arithmetic operations of addition and multiplication in a VLSI environment are analyzed for area-time efficiency. It is shown that some schemes for addition and multiplication, although good for stand-alone designs, fail to provide both area and time efficiencies simultaneously. Solutions that yield area-time efficient practical implementations of these arithmetic functions are described.