Unequal-Cells-Based GaN HEMT Doherty Amplifier With an Extended Efficiency Range

This paper reports the advanced design of an extended GaN HEMT Doherty power amplifier (DPA). For high efficiency over a wide output power range, the DPA is designed using two cells with uneven saturation power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ). A cell with lower P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> is used as the carrier cell. For experimental validations, the carrier and peaking cells are designed and implemented with 25-W GaN HEMTs at world interpretability for microwave access (WiMAX) band of 2.6 GHz, and then show the P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> of 40.9 dBm and 43.8 dBm, respectively. For the proposed DPA, the continuous wave results show the power-added efficiency (PAE) of 37.5% at an output power of 36 dBm (10-dB back-off power from P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ). For a WiMAX signal, the PAE of 36.9% with an relative constellation error (RCE) of -31 dB is obtained at 36 dBm, which is 7.8% improvement compared to the conventional DPA.

This letter reports a high-efficiency gallium nitride (GaN) high-electron mobility transistor (HEMT) Doherty power amplifier (DPA) based on the class-E topology for wideband code-division multiple-access (WCDMA) applications. The class-E topology is employed as the carrier and peaking cells of the Doherty configuration. For validations, the proposed DPA is designed and implemented with 25-W GaN HEMTs at 2.14 GHz. For the proposed DPA, the power-added efficiency (PAE) and drain efficiency of 56.1% and 61.2% are achieved at 40 dBm (6-dB backoff power from Psat) for a continuous wave. For a 1-carrier WCDMA signal, the PAE of 44.8% is obtained with an adjacent channel leakage ratio (ACLR) of -31 dBc at 37 dBm, which is an 8.9% improvement over the conventional DPA with an ACLR of -36.4 dBc.

This paper presents a linear Doherty power amplifier (DPA) in microstrip technology designed at 1.7 GHz, for long-term evolution (LTE) applications. The DPA has been implemented using a low-cost GaAs HEMT with adoption of different drain bias voltage for main and auxiliary amplifiers to increase the overall gain. Measured performance of the proposed DPA across 1.48–1.83 GHz shows an output power of 31.5 dBm with 60% power added efficiency (PAE) at the 1-dB compression point (P1dB). The PAE is maintained higher than 50%, over 6 dB of output back-off range, and higher than 30% over 10 dB output power back-off. Moreover, the linearity performance of the designed DPA in terms of IMD3 is tested by applying a two-tone signal to the input of DPA which shows the IMD3 of less than −27 dBc at an output power of 31.5 dBm and −33 dBc at about 6 dB back-off power.

In this article, we propose the wideband digital predistortion (WDPD) for a highly linear and efficient GaN HEMT Doherty power amplifier (DPA). The WDPD is composed of the memory less DPD and the memory system, which compensates for the memory effects to achieve a highly linear wideband performance. The 11th‐memoryless polynomial characterizes the behavioral model of the DPA. The AM/AM and AM/PM lookup tables and the coefficients of the memory system are determined by the Recursive Least Square algorithm. For a 2‐FA WCDMA signal with 10 MHz carrier spacing at 2.14 GHz, the adjacent channel leakage ratio at ±10 MHz offset are improved over −50 dBc without the efficiency degradation at an output power of 36 dBm. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 484–487, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24951

In this letter, a new Doherty power amplifier having the ideal harmonic termination condition that has been usually ignored is proposed. A defected ground structure (DGS) is adopted on the ground pattern of the output lambda/4 impedance inverter of the carrier amplifier and output offset transmission line of the peaking amplifier that are essential for proper load modulation operation of a conventional Doherty amplifier. As a result of the second and third harmonic termination, excellent improvement in power added efficiency (PAE), gain, maximum output power as well as linearity is obtained. The acquired improvements in gain, maximum output power (P1 dB), PAE, and adjacent channel leakage ratio to wideband code division multiple access 2FA signal are 0.33 dB, 0.42 dB, 12.7%, and 5.1 dB, respectively. Moreover, physical length of microstrip line is shortened fairly by DGS, therefore the whole amplifier circuit size is considerably reduced

This brief presents a three-way Doherty power amplifier (DPA) with a symmetric structure in terms of the output power capacities between the carrier and peaking amplifiers for high efficiency and linearity. Based on the analysis for the efficiency peak at the output power back-off, a symmetric structure was adopted to have higher overall efficiency for the modulated signal. Through the optimized bias condition for the two peaking amplifiers, the proposed three-way DPA can be linearized in the wide output power range. To validate the proposed scheme, a three-way DPA was designed and implemented using a 60 W GaN-HEMT for the carrier amplifier and two 30 W GaN-HEMTs for the peaking amplifiers. Using a 2.14 GHz long-term evolution downlink signal with a peak-to-average power ratio of 6.5 dB, the implemented symmetric three-way DPA exhibited a drain efficiency (DE) of 33.7% and an ACLR of -38 dBc at an average output power of 41.4 dBm. Compared to the condition with the same bias for the peaking amplifiers, the DE and average output power were improved by 8.0% and 2.4 dB for the given ACLR of -38 dBc, respectively.

This paper proposes a Real-Valued Time-Delay Recurrent Radial Basis Function (RVTDRRBF) model suitable for dynamic modeling of the strongly nonlinear behaviors of the Doherty Power Amplifiers (DPAs). This model has four Tapped Delay Lines (TDLs), which account for the memory effect of the DPA. The structure of the RVTDRRBF model is simpler than the traditional FeedForward Neural Networks (FFNNs) model. Weights and centers of the proposed model can be resolved by the Orthogonal Least Square (OLS) and Singular Value De-composition (SVD) algorithm. A three-carrier Wideband Code Division Multiple Access (WCDMA) signal is taken as the test signal. The simulation results in frequency-domain and time-domain for a DPA with 51 dBm output illustrate a good agreement between the RVTDRRBF model and measurement data. Moreover, comparing the Normalized Mean Square Error (NMSE) of RVTDRRBF model, memory polynomial model and RVTDRBF model, it can be noticed that the proposed RVTDRRBF model is more accurate than the RVTDRBF model and the memory polynomial model in modeling the strong dynamic nonlinearity of the DPAs.

This paper presents a Doherty power amplifier (DPA) controlled by the optimized bi-level supply modulator to improve an overall efficiency. By utilizing the supply modulation method determined by the probability density function (PDF) of an interest signal, an estimated average efficiency can be improved as much as 8.5 % compared with that of conventional DPA. For the verification the proposed DPA using commercial 120 W GaN devices has been devised. The experimental results show that the proposed DPA delivers a drain efficiency (DE) of 53.8 % and power added efficiency (PAE) of 50 %, with a gain of 11.8 dB at an average output power of 34.7 W for a 2.65 GHz 10 MHz 3G LTE signal with a 9 dB peak-to-average power ratio (PAPR). The measure result reveals that the DE of proposed DPA is 6 % higher than that of conventional one.

This paper presents the simulation of a highly efficient Doherty power amplifier using second harmonic management. The performances of power amplifiers are really affected by the second harmonic. Power amplifier benefits from proper management of the second harmonic load impedance. Similarly, harmonic control can also be applied into Doherty configuration for enhancing performances. A harmonic control led Doherty power amplifier which works at 1.8 GHz is constructed in this work. The simulation results indicate the designed Doherty power amplifier delivers a the drain efficiency of 70.4% at 6 dB power back-off, a drain efficiency of 78.1% at saturation power level, and a maximum output power of 44 dBm with a saturation gain of13 dB.

This letter presents an approach to maximize the output power and efficiency of a Doherty power amplifier (PA). The conventional carrier PA having match, used in a symmetric Doherty PA, does not deliver the saturated high efficiency at the 6 dB back-off power but at the 5.5 dB back-off power due to the knee voltage effect. To solve the problem, the gate biases of the carrier and peaking PAs are adapted. The gate bias voltage of the carrier PA is optimized for a higher peak output power, delivering a 3 dB larger peak power at match. That of the peaking PA is also optimized to have the same peak power of the carrier PA. A Doherty PA with the concept is designed using a 45 W gallium nitride (GaN) high electron mobility transistors (HEMT) for the carrier and peaking cells at 1.94 GHz. The measured average output power, drain/power-added efficiencies and gain are 44.35 dBm, 60.5/57.2%, and 12.75 dB for a 10 MHz long term evolution (LTE) signal with a 6.5 dB peak-to-average power ratio (PAPR).

We present two simplified Doherty power amplifier (DPA) structures to eliminate a quarter-wavelength impedance inverter used in the conventional DPA structure. The simplified DPA structures reduce the number of the impedance inverters, therefore they can be easily adopted in the broadband/multi-band applications of the DPA. To prove the design concept of the simplified DPA structures, a dual-band DPA based on one of the proposed structures is designed and fabricated. The designed dual-band DPA provides 76.3% drain efficiency (DE) at the full output power (39.8 dBm) and 54.5% DE at 6 dB of output power back-off (OBO) at 600 MHz, and it also provides 54% drain efficiency (DE) at the full output power (40.2 dBm) and 37% DE at 6 dB of output power back-off (OBO) at 1000 MHz.

In this work, a Doherty power amplifier is presented for IMT-Advanced system at 450–470MHz frequency band. An imperfect Quarter-wave transmission line, which consisted of two shunt capacitors and a series microstrip line, is adopted to replace the bulky impedance inverter quarter-wave transmission line for designing the Doherty power amplifier (PA). Both the traditional and proposed structures for the Doherty power amplifiers were implemented. Comparing with the traditional Doherty amplifier, the size of the circuit and the manufacturing costs are decreased obviously. The measurement results of the proposed Doherty PA exhibit good performance as well as the traditional Doherty power amplifier. For a input signal with a 7.8dB Peak to Average Power Ratio (PAPR), the measured drain efficiency of the proposed Doherty power amplifier is 48.5% at an average output power of 43.0 dBm, which is a 7.8dB backed — off the peak output power. Moreover, in order to improve the linearity of the proposed Doherty power amplifier, the augmented Hammerstein and polynomial predistorter are used to linearize the proposed Doherty power amplifier. After digital predistortion, the adjacent channel leakage ratio (ACLR) reaches −45.5dBc at an average output power of 43.0 dBm, which can satisfy the requirements of the IMT-Advanced systems.

We propose a new efficiency enhancement technique of Doherty power amplifiers (DPAs) using virtual short stub. In this technique, the peaking amplifier branch was utilized as an inductive short stub at output power combing point at low power level. Using this technique, it is possible to transform the low-power load impedance seen from the carrier amplifier into higher impedance than that of classical DPAs. This leads to efficiency enhancement at larger power back-off than conventional DPAs (>6dB). The relation of efficiency enhanced level and the circuit topology for DPAs with the virtual short stub are analytically derived. The proposed technique was experimentally verified by fabricating a 3.5 GHz 40 Watt Doherty power amplifier using GaN HEMTs. An average drain efficiency of 51% and adjacent power leakage ratio of −50 dBc was obtained using 10MHz LTE test signals with 8.5dB peak-to-average power ratio.

In this article, a novel high‐efficient Doherty power amplifier (DPA) is designed for linearity improvement from 2.1 to 2.4 GHz. The proposed DPA employs a pair of anti‐coupled lines loaded with a stepped impedance resonator to replace the λ/4 transmission line in the conventional DPA for harmonic suppression, phase compensation, and impedance transformation. The DPA is simulated, fabricated, and measured. As the measured results show, in the 2.1‐2.4 GHz band, the saturated output power is between 43.2 and 44.5 dBm with the saturated gain level between 10.2 and 11.5 dB. The saturated drain efficiency (DE) is between 60% and 70% with DE at 6 dB output power back‐off between 38% and 50%. Compared with the conventional DPA, the third‐order intermodulation distortion is reduced by 20 dB. The efficiency and gain have also been improved. The proposed DPA is feasible and applicable in modern wireless communication systems.

ABSTRACTIn this article, we present a simplified Doherty power amplifier (DPA) architecture for the easy implementation of dual‐band operation. The proposed DPA structure eliminates the 35 Ω quarter wavelength impedance inverters used in the conventional DPAs by matching the output impedances of the carrier and peak amplifiers of the DPA to other values (e.g., 100 Ω). The electrical lengths of the offset line and the phase compensation line are carefully chosen to enhance the Doherty effect (high efficiency at back‐off power level) at two assigned frequency bands. Broadband matching networks are also designed to increase the operation bandwidths at the two designed bands. To prove the design concept, a dual‐band DPA is designed and measured. In the first frequency band (550–650 MHz), the designed DPA provides 60.6–76.3% drain efficiency (DE) at full output power, 46–54.9% DE at 6 dB of output power back‐off (OBO); in the second frequency band (950–1050 MHz), the designed DPA provides 51.4–61.2% DE at full output power, 35–38% DE at 6 dB of OBO. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:953–956, 2015