Using Six Sigma Techniques to Optimize Cleaning in Class III Electronics

Constituents and performance of no-clean flux for electronic solder

As highly dense circuit assemblies continue to advance at a rapid pace, the removal of process residues is ever more necessary. Low residue no-clean residues did not require cleaning on assemblies with larger spacing between conductors. As the distance between conductors narrow, residues under component gaps pose a reliability risk. Additionally, the transition to lead-free alloys with tighter component densities requires flux residue innovations that can withstand higher reflow temperatures. Traditional cleaning agents and cleaning equipment may not be able to remove these harder to clean flux residues from extremely small geometries. Increased circuit functionality is accomplished using bottom termination surface mount components. As components reduce in size, the distance from the board to the underside of the component reduces. Flux residues bridge conductors making cleaning highly difficult. One of the most challenging issues is the selection of an appropriate cleaning process that will clean flux residues under these extremely tight geometries. Cleaning agents must be designed to remove strong covalent (hydrophobic) and weak ion (hydrophilic) bonds. Cleaning machines must be designed to move the cleaning agent to the source of the residue and either extract or create a flow channel to remove residues under component gaps. Recent solvent and aqueous cleaning agent and cleaning equipment innovations have been developed to bridge this gap.To achieve the process objective, cleaning agent and cleaning equipment suppliers collaborate with assemblers to develop improved cleaning processes. Topics Covered: • Chemical Properties of Residues • Solvent and Aqueous Cleaning Agents Innovations Designed to Remove Residues • Cleaning Equipment Innovations Designed to Remove Flux Residues under Bottom Termination Components • Integrating Cleaning Agent and Cleaning Machine • Controlling the Process Who Should Attend: • Circuit Assembly Designers • Process Engineers • Quality Control Engineers • Environmental Engineers Instructor Bio: Mike is one of the joint founders and CTO of Kyzen Corporation. He is an active researcher and innovator in the precision cleaning field. Mike chaired the IPC Cleaning & Alternatives Handbook, IPC Stencil Cleaning Handbook, and two IPC/SMTA Cleaning and Conformal Coating Conferences. Mike has published over 100 tech papers and received a number of awards in his field of expertise. Mike holds four earned degrees, including a Doctorate of Business Administration from the University Of Phoenix School Of Advanced Studies. Files Included Recorded Presentation Parts 1 and 2 (On Demand) Slides On Demand Webinar

Flip-chip technology has become increasingly prevalent within the electronics industry due to its lower cost, increased package density, improved performance while maintaining or improving circuit reliability, and increased I/O density. This technology is a method for interconnecting semiconductor devices such as IC chips and MEMS to external circuitry with solder bumps that have been deposited onto the chip pads. However, solder bump technology has proven to be problematic below 125µm pitch as it is challenging to manufacture and assemble. As pitch is reduced, both standoff height and joint reliability decrease, and the risk of shorts are increased. Given this, traditional solder bumps are being replaced by copper pillar technology. Used as first-level interconnect, copper pillar technology is increasing in popularity. Copper pillar technology has been documented to be efficient to pitches of 80 µm and appears to be promising down to pitches of 40µm. Along with reduced pitches, copper pillar brings several other benefits, including improved electrical performance. This technology is becoming popular since it allows for smaller devices, greater control of standoff height and reduces the number of package substrate layers which reduces cost. Devices utilizing copper pillar technology have more interconnects per surface area resulting in tighter pitch and lower standoffs heights. As standoff height reduces, flux residues have less area to outgas during reflow. For that reason, there is a critical need to investigate the conditions that would be required to successfully remove flux residues to ensure the functionality and reliability of the final product. Flux residues can affect reliability, especially with respect to underfill in two different ways. Firstly, if present on the solder bump, substrate or die, thin films of flux residue can significantly reduce interfacial adhesion between the underfill and the surfaces. Once the underfilled device is stressed by thermal shock, humidity or other factors, the underfill delaminates from the surface, and a gap can be detected using acoustic microscopy. Secondly, fluxes can affect reliability by physically impeding the flow of underfill material. Flux residue buildup in the gap between bumps or between the die and the substrate can narrow the gap to a point where the underfill cannot flow or the edges flow faster, encapsulating air and creating a void. To ensure a void-free underfill, homogenous wetting of the underfill must occur on all surfaces. If wetting is not homogeneous, voids in the uncured underfill may translate into reliability problems later. The study involved using straight DI-water and novel low-concentration alkaline cleaning agent on copper pillar bumped flip chips. The challenge was to effectively clean flux residues underneath these components. The outcome of this study could provide a benchmark for conducting further studies involving bump pitch lower than 15 µm and denser packages including 2.5Ds and 3Ds. The cleaning assessment methodologies employed analytical/functional testing including FTIR, Ion Chromatography, SEM/EDX, Thermal Cycling (TC) Test, Underfill Test, High Temp Storage Life (HTSL) Test and Moisture Sensitivity Level 3 (MSL-3) Testing.

첨단 전자기기에 사용되는 전자부품의 크기와 접속피치가 감소하면서 리플로우 공정 후 플럭스 잔사의 세정이 어려워짐에 따라 무세정 솔더 페이스트에 대한 요구가 증가하고 있다. 본 연구에서는 SAC305 솔더분말과 에폭시 레진을 주성분으로 하는 경화성 플럭스를 혼합하여 제조한 에폭시 경화형 솔더 페이스트에 대하여 리플로우 공정성, 플럭스 잔사의 부식성, 솔더볼 및 보드레벨 BGA 패키지 솔더 접합부의 기계적 거동을 기존 로진계 솔더 페이스트와 비교하여 평가하였다. 에폭시 경화형 솔더 페이스트는 솔더 접합부 주변에 경화물 필렛을 형성한 것으로 보아 플럭싱 작용에 의해 솔더 접합부가 형성된 이후에 경화반응이 진행되는 것을 확인할 수 있었으며, 동판에 대한 젖음성 시험을 통해 기존상용 솔더 페이스트 정도의 납퍼짐성을 갖는 것을 알 수 있었다. 리플로우 후 동판에 대한 고온 고습 시험을 통해 에폭시 경화형 솔더 페이스트는 동판 부식을 전혀 발생시키지 않는 것으로 나타났는데, 이는 FT-IR 분석결과 에폭시 경화반응을 통해 단단히 고정된 결과로 생각되었다. 볼전단, 볼당김 및 다이전단 시험 결과, 솔더 접합부 주변에 형성된 경화물 필렛은 솔더 표면과 접착본딩을 형성하며, 다이전단강도를 15~40% 정도 향상시키는 것으로 보아 에폭시 경화형 솔더 페이스트는 플럭스 잔사 세정공정의 생략과 함께 솔더 접합부 보강효과를 통해 패키지 신뢰성 향상에도 기여할 수 있을 것으로 생각되었다. With difficulties during the cleaning of reflow flux residues due to the decrease of the part size and interconnection pitch in the advanced electronic devices, the need for the no-clean solder paste is increasing. In this study, an epoxy curable solder paste was made with SAC305 solder powder and the curable flux of which the main ingredient is epoxy resin and its reflow solderability, flux residue corrosivity and solder joint mechanical properties was investigated with comparison to the commercial rosin type solder paste. The fillet shape of the cured product around the reflowed solder joint revealed that the curing reaction occurred following the fluxing reaction and solder joint formation. The copper plate solderability test result also revealed that the wettability of the epoxy curable solder paste was comparable to those of the commercial rosin type solder pastes. In the highly accelerated temperature and humidity test, the cured product residue of the curable solder paste showed no corrosion of copper plate. From FT-IR analysis, it was considered to be resulted from the formation of tight bond through epoxy curing reaction. Ball shear, ball pull and die shear tests revealed that the adhesive bonding was formed with the solder surface and the increase of die shear strength of about 15~40% was achieved. It was considered that the epoxy curable solder paste could contribute to the improvement of the package reliability as well as the removal of the flux residue cleaning process.

Flux materials are ubiquitously utilized in the microelectronics industry during back-end processing. The Cu oxides or organic solderability preservatives present on Cu posts used in flip-chip packages must be removed by flux before solder reflow and die attachment to ensure a quality connection between the substrate and the die. However, flux residues can cause solder bridging, which renders the device useless. These residues must be studied in situ at the buried interface to determine fundamental interactions and how the residues can be eliminated. In this paper, model flux residues were investigated at the surface and the buried epoxy interface with sum frequency generation vibrational spectroscopy. Glutaric acid. served as the model flux, simulating fluxes that use dicarboxylic acids as one of the main components of the fluxing agent. It was found that the flux residues greatly change the buried interface on both Cu and silica surfaces, which affects properties such as adhesion. It was also observed that the fluxes require long washing times before they are completely removed. This paper is a step forward in flux residue analysis and will help the industry better understand molecular-level details of commonly used processes.

Circuit / System PCB designer's objective is to increase device functionality in a smaller form factor with a higher density electronic layout. Higher density and smaller form factor components are driving the industry toward a higher risk situation in intermittent electronic performance. Voltage leakage and even current leakage can lead to signal integrity loss and even flip bit issues or drops in processing commands. As the density increases and the miniaturization drops in size and spacing so does the increase in failure mode opportunities for signal integrity / signal loss. The spacing between conductors and pads in the past has been our friend and saving grace by giving us greater insulation between these conductors and pads. Even the standoff heights within the Z-Axis of miniaturized components are approaching one mil. This drop in z-axis means there is smaller cubic volume area to outgas volatiles or insure the volatization / boil off effect of flux additives such as inhibitors (against oxidation / corrosion), activators (promotes wetting) and thermal stabilizers (insures fluxing action at peak reflow temps) during reflow, flux residues can become entrapped under the component itself in a state that has not fully deactivated. Mobile ions within the flux residues form leakage currents and or voltages, especially when the device is operating within humid environments. Flux residue can contain halide / ionic materials which, when trapped under a part can lead to shorts across adjacent pads, or voltage/current leakage pathways. Companies who require devices to meet long term reliability / warranty expectations need an improved industry test specification that allows for an accurate risk assessment. The problem is that the risk assessment is a multi-variable issue influenced by flux type, flux make up (activators and inhibitors), activation temperature, component type and placement; the type and criticality of the circuit in which the component is operating in, wash characteristics if not a noclean flux system, solder paste volume, PCB cleanliness and component contamination. Current measures of “clean” do not indicate if the product is clean enough in a critical area, which is what we hope to do. The goal is to design a test and test vehicle which encompasses the challenges of today so the System Design Engineer can define and characterize risk within his/her electronic assembly for long term reliability associated with cleanliness of the finished electronic assembly and final system warranty expectation. This is a tall order but there is a concern within critical industries such as Military, Medical, Automotive, Aerospace and safety critical industrial applications and industries to better define the risk and measure the risk associated with cleanliness. Cleanliness is a broad term for the mitigation and measurement of Electrochemical Migration (ECM) and pitting and creep corrosion, and general surface insulation breakdown due to free ionics. This paper will report ongoing research to study these multivariant issues using a new test vehicle with sensors placed under and near bottom terminations such as QFN and LGA components. The test vehicles are designed to track impedance where it matters most. The goal of this research is to develop an improved method for studying multivariables that may impact circuit / component reliability. This is not a single event / variable equation but a very complex multi - variable problem with varying degrees of interaction. Some of the main variables are processing equipment temperature controls / profiles; construction of the flux system and its chemical formulation; volume of flux residue remaining; and the type of component and its design as well as the plating finishes used on pads as well as the type of solder alloys used. This list was not all inclusive but gives an insight to the multi-variable problem statement. Data findings, inferences from the data findings, and recommendations will be documented and presented

PurposeThe purpose of the present study was to review the thermo-mechanical challenges of reflowed lead-free solder joints in surface mount components (SMCs). The topics of the review include challenges in modelling of the reflow soldering process, optimization and the future challenges in the reflow soldering process. Besides, the numerical approach of lead-free solder reliability is also discussed.Design/methodology/approachLead-free reflow soldering is one of the most significant processes in the development of surface mount technology, especially toward the miniaturization of the advanced SMCs package. The challenges lead to more complex thermal responses when the PCB assembly passes through the reflow oven. The virtual modelling tools facilitate the modelling and simulation of the lead-free reflow process, which provide more data and clear visualization on the particular process.FindingsWith the growing trend of computer power and software capability, the multidisciplinary simulation, such as the temperature and thermal stress of lead-free SMCs, under the influenced of a specific process atmosphere can be provided. A simulation modelling technique for the thermal response and flow field prediction of a reflow process is cost-effective and has greatly helped the engineer to eliminate guesswork. Besides, simulated-based optimization methods of the reflow process have gained popularity because of them being economical and have reduced time-consumption, and these provide more information compared to the experimental hardware. The advantages and disadvantages of the simulation modelling in the reflow soldering process are also briefly discussed.Practical implicationsThis literature review provides the engineers and researchers with a profound understanding of the thermo-mechanical challenges of reflowed lead-free solder joints in SMCs and the challenges of simulation modelling in the reflow process.Originality/valueThe unique challenges in solder joint reliability, and direction of future research in reflow process were identified to clarify the solutions to solve lead-free reliability issues in the electronics manufacturing industry.

Electronic assembly mean time to failure studies have reported various forms of corrosion from residues left uncleaned under Bottom Termination Components. Some of the concerns with miniaturized components are decreased conductor distance, low standoff heights, and residues bridging conductors. Assemblers who decide to clean want assurance that the residues will be removed under bottom termination components. Numerous factors must be considered when engineering a cleaning process that is capable of removing flux residues from under Bottom Termination Components. Four key factors to an ideal cleaning condition are (1) PCB Board Design, (2) Solder Paste / Flux Selection, (3) Cleaning Agent Selection, and (4) Cleaning Machine Selection. The purpose of this research study is to evaluate the cleanability of low residue flux residues under Bottom Termination Components in batch spray in air cleaning tools. The study will report flux removal efficiency of aqueous cleaning agents in various batch cleaning tools. From the data findings, inferences will be made as to the important features that provide a wide cleaning process window.

White residue formation after soldering is one of the most complex problems in cleaning electronic assemblies. The visual appearance of flux residue has much to do with the flux composition and solder profile. White residue is affected by a wide range of electronic assembly materials including all flux types, heat exposure during soldering and before cleaning, component spacing and pitch, solder masks, cleaning agent, wash processing conditions and mechanical cleaning energy. The ideal state, specifically for no-clean processes, is a clear translucent solid, with active ingredients fully reacted and benign. White residue left after the cleaning process is commonly the result of extracting and removing only some soluble ingredients of the residue while leaving behind an insoluble white crystal. The most effective method for preventing white residue is controlling the upstream soldering process, post soldering heat exposure before cleaning and optimizing cleaning process variables. Over-heating the assembly during and after the soldering process can burn, char, cross-link and eventually polymerize flux residues. Changing the residue properties can lead to partial cleaning. The second key factor that contributes to white residue is the wash process. The critical variables for controlling the process are the cleaning agent, wash time, wash temperature, wash concentration, and impingement energy. The purpose of this research paper is to provide participants with an improved understanding of how controlling the assembly process and wash parameters reduce the occurrence of white residue.

10 - Cleaning soldered assemblies

The increasing demand for high performance integrated circuit devices has been leading the development of 3-D stacking technologies. One of the state-of-art 3-D stacking methods is the through silicon via (TSV) interconnection which may facilitate very high density memories or ASIC modules. Industrial mass production and academic research to use the through silicon via(TSV) in the 3D interconnection has brought the matured technology for forming the TSV in the chip. However, former method using flux and underfill for interconnection between chips have several drawbacks such as flux residues or voids trap along the bonding interface causing reliability issues. As one of the solutions, chip interconnection using Cu/SnAg bump and non-conductive film has been gaining a lot of interest as the one of the promising ways for 3D TSV interconnection. In this paper, a study is made for the relationship between the viscosity of pre applied non-conductive film and loading force to predict the gap change. The existing theories are adapted to predict the gap change of a real chip and a substrate during bonding with using simplified model. A gap changes from real bonding of dies were matched to check the validity of prediction. As a summary, 3D-TSV vertical interconnection using Cu/SnAg bump and wafer-level NCFs was theoretically and experimentally investigated. Through the theoretical investigation, bondings were explained using the rheological properties of NCFs, chip size, and bonding parameters. And the real chip bonding was matched to the prediction from the theory. Therefore, chip bonding using Cu/SnAg bump and NCFs could be the promising solution for the fine pitch TSV interconnection.

As advanced packaging continues to drive towards heterogeneous integration, new materials need to be developed to address the many challenges faced in the assembly process. This presentation will focus on innovative materials for advanced packaging, particularly for small form factor modules, including novel flux formulations for flip chip attach that are compatible with underfill and molding compound, an adhesive agent for fluxless soldering with a formic acid atmosphere, solders with various temperatures for hierarchical soldering. The technology drives toward increased functionality, better efficiency, and higher power density; advanced packaging silicon chip/die size is now bigger, with densely packed interconnect, tighter pitch, and smaller bumps. Some of the common issues we observed due to these are warpage-induced open joints from the big and thin die, flux residue removal challenges due to the tight spacings, and thermal-induced reliability issues. Novel flux formulations and adhesive agents for wafer/die bonding are needed, and interactions between the flux material and various dielectric materials on the wafer need to be better studied. The shift towards using semiconductor-grade ultra-low residue no-clean flip-chip fluxes, which eliminates the cleaning process, is one of the solutions for overcoming these challenges. Another possible solution, studied in recent years, is using a near-zero residue fluxless adhesive agent to hold the die in place while reflowing in a formic acid reflow atmosphere. The development of new solders is also a critical enabler for heterogeneous integration. If there are different reflow cycles that require a solder hierarchy, alloys with varying melting temperatures may be needed for SIP. In addition, lower melting-temperature solders can provide better warpage control, especially for thin die and substrate, as well as for heat-sensitive sensors, die, or substrate that require low-temperature processing. Alloys with enhanced reliability are also needed for certain SIP modules. In summary, proper selection and application of interconnect materials for various assembly processes is crucial to ensuring high production yield for the assembly process of advanced packaging and SIP application.

A new type of package model is introduced, which allows to take into account the effect of external structures, such as PCB traces and ground plane, by limiting at the same time the disclosure of internal details of the package. The model is verified with a scaled quad flat package (QFP) and two different printed circuit board (PCB) patterns, but the general procedure should be applicable to other types of package.

For quad flat packages (QFP256), lead-free soldered joints reliability in service is a critical issue. In this paper, soldering experiments of quad flat package (QFP256) devices were carried out by means of infrared reflow soldering system with Sn–3.8Ag–0.7Cu and Sn–3.8Ag–0.7Cu–0.03Ce lead-free solders, respectively, and the mechanical properties of micro-joints of the QFP devices were tested and studied by STR micro-joints tester. The results indicate that the tensile strength of Sn–Ag–Cu–Ce soldered joints is better than that of Sn–Ag–Cu soldered joints. In particular, the addition of trace Ce to the Sn–Ag–Cu solder can refine the microstructures and decrease the thickness of the intermetallic compound layer of Sn–Ag–Cu solder alloys. In addition, the stress–strain response of Sn–Ag–Cu/Sn–Ag–Cu–Ce soldered joints in quad flat packaging was investigated using finite element method based on Garofalo–Arrhenius model. The simulated results indicate creep distribution of soldered joints is not uniform, the heel and toe of soldered joints, the area between soldered joints and leads are the creep concentrated sites. The creep strain of Sn–Ag–Cu–Ce soldered joints is lower than that of Sn–Ag–Cu soldered joints.

Advanced packaging is a promising solution to exploit the benefits of scaling down by developing new architecture, reducing communication distance and achieving higher packaging density. To attain this, standardization, new processing techniques, co-design tools and multi-physics simulation techniques are critical to advanced packaging technology. Diamond in advanced packaging as well as heterogenous integration of diamond with dielectrics and semiconductors is crucial in achieving advanced packaging for high power and high temperature applications. Among wide bandgap semiconductor materials, diamond demonstrates extreme hardness, chemical inertness, high thermal conductivity, high hole and electron mobility, high dielectric strength and high breakdown strength, and has the widest band gap. These properties are ideal for high power amplifiers and switches, as well as for heat sinks for advanced packaging. The present review will describe our approach that combines the novel CVD growth techniques and delta doping concepts already demonstrated in order to achieve innovative diamond FETs or HEMTs for high power applications. Diamond is heterogeneously integrated with graphene as well as other wide bandgap materials in order to achieve state of the art results in thermal management.