Using timed Petri net to model instruction-level loop scheduling with resource constraints

The low power register scheduling and allocation algorithm is concerned with minimum switching activity and low power multiple voltages. The proposed algorithm executes low power scheduling to reduce switching activity using a shut down technique by the creation of a data flow graph (DFG) from the VHDL description. Also, the low power register allocation algorithm determines the minimum register after the life time analysis of all variables. It minimizes the switching activity using a graph coloring technique for low power consumption. Finally, the total power is reduced by using the low power multiple voltage. The proposed algorithm proves the effect through various filter benchmarks to adopt a low power register scheduling and allocation algorithm considering resource constraint at multiple voltage.

The emerging technology of the System-on-Chip (SoC) is presenting new challenges at both the hardware and software stages of the design process. At present, system software engineers, e.g. high-level programming language (e.g. C/C++) compiler writers for processor cores, are working at the abstraction level of instruction set architecture (ISA) and its compiler optimization. On the other hand, the hardware engineers for the processor cores and other devices are working at a lower level abstraction level, e.g. RTL level, and using hardware description languages (e.g. VHDL, Verilog) and associated silicon compiler tools. Problems of communication gaps between the two world continue to exist due to the different abstraction levels, and the use of different design languages, incompatible tools and fragmented design flow, etc.In this talk, we discuss such gaps with examples illustrating the limits of optimization that can be performed from the hardware/software alone. With the demand of aggressive exploitation of instruction-level parallelism with high-performance uniprocessor core as well as the need of multiprocessor cores - such gaps must be bridged. Such optimization includes instruction scheduling; register allocation, loop scheduling, locality optimization, etc. Such gaps also affect software debugging (including performance debugging) as well as hardware verification.We briefly outline solution challenges and opportunities in this direction.

Real-time system is playing an important role in our society. For such a system, sensitivity to timing is the central feature of system behaviors, which means tasks in the system are required to be completed before their deadlines. Currently, almost all the practical real-time systems are equipped within multiple processors, for which the schedule synthesis to make sure that all the tasks can be completed before their deadlines is known to be an NP complete problem. In this paper, to solve the scheduling problem, we propose a scheduling method based on satisfiability modulo theories (SMT). In the method, the problem of scheduling is treated as a satisfiability problem. The key work is to formalize the satisfiability problem using first-order language. After the formalization, a SMT solver (e.g., Z3, Yices) is employed to solve such a satisfiability problem. An optimal schedule can be generated based on a solution model returned by the SMT solver. Moreover, in the SMT-based scheduling method, we define the scheduling constraints as system constraints and target constraints. Such design makes the proposed method apply more widely compared with existing methods.

Multi-project Time-cost Optimization in Critical Chain with Resource Constraints

Clustered ILP processors are characterized by a large number of non-centralized on-chip resources grouped into clusters. Traditional code generation schemes for these processors consist of multiple phases for cluster assignment, register allocation and instruction scheduling. Most of these approaches need additional re-scheduling phases because they often do not impose finite resource constraints in all phases of code generation. These phase-ordered solutions have several drawbacks, resulting in the generation of poor performance code. Moreover the iterative/back-tracking algorithms used in some of these schemes have large turning times. In this paper we present CARS, a code generation framework for Clustered ILP processors, which combines the cluster assignment, register allocation, and instruction scheduling phases into a single code generation phase, thereby eliminating the problems associated with phase-ordered solutions. The CARS algorithm explicitly takes into account all the resource constraints at each cluster scheduling step to reduce spilling and to avoid iterative re-scheduling steps. We also present a new on-the-fly register allocation scheme developed for CARS. We describe an implementation of the proposed code generation framework and the results of a performance evaluation study using the SPEC95/2000 and MediaBench benchmarks.

Continuing medical education (CME) emerged at the start of the 20th century as a means of maintaining clinical competence among health care practitioners. However, evidence indicates that CME is often poorly developed and inappropriately used. Consequently, there has been increasing interest in the literature in evaluating wider contexts at play in CME development and delivery. In this article, the authors present a unified theoretical framework, grounded in learning theories, to explore the role of contextual factors in public health CME for health care practitioners. Discussion with pedagogical experts together with a narrative review of learning theories within medical and social science literature informed the framework's development. The need to consider sociocultural theories of learning within medical education restricted suitable theories to those that recognized contexts beyond the individual learner; adopted a systems approach to evaluate interactions between contexts and learner; and considered learning as more than mere acquisition of knowledge. Through a process of rigorous critical analysis, two theoretical models emerged as contextually appropriate: Biggs principle of constructive alignment and Bronfenbrenner bioecological model of human development. Biggs principle offers theoretical clarity surrounding interactive factors that encourage lifelong learning, whereas the Bronfenbrenner model expands on these factor's roles across multiple system levels. The authors explore how unification into a single framework complements each model while elaborating on its fundamental and practical applications. The unified theoretical framework presented in this article addresses the limitations of isolated frameworks and allows for the exploration of the applicability of wider learning theories in CME research.

In this paper, the problem of parallel loop scheduling for heterogeneous networks of workstations is discussed. A practical network of workstations is heterogeneous where computing power varies in different composing workstations. A simple loop scheduling technique is insufficient in exploiting maximum computing power of such a system. We propose a fundamental idea for a performance prediction tool to gauge the relative computing power among composing workstations so that parallel performance of a program run on a given network can be predicted. In view of the performance prediction results, a loop scheduling approach is then incorporated into the system to achieve close-to-optimal parallel performance. Examples running benchmark programs demonstrate a significant gain from the proposed approach over traditional scheduling approaches.

Many high-performance DSP processors employ multi-bank on-chip memory to improve performance and energy consumption. This architectural feature supports higher memory bandwidth by allowing multiple data memory accesses to be executed in parallel. This paper studies the scheduling and assignment problem on minimizing the total energy consumption while satisfying timing constraint with heterogeneous multi-bank memory for applications with loop. An algorithm, TASL (Type Assignment and Scheduling for Loops), is proposed. The algorithm uses loop scheduling and assignment with the consideration of variable partition to find the best configuration for both memory and ALU.

A synthesised review of pandemic-driven consumer behaviours and applied theories: Towards a unified framework

Register allocation is a much studied problem. A particularly important context for optimizing register allocation is within loops, since a significant fraction of the execution time of programs is often inside loop code. A variety of algorithms have been proposed in the past for register allocation, but the complexity of the problem has resulted in a decoupling of several important aspects, including loop unrolling, register promotion, and instruction reordering. In this paper, we develop an approach to register allocation and promotion in a unified optimization framework that simultaneously considers the impact of loop unrolling and instruction scheduling. This is done via a novel instruction tiling approach where instructions within a loop are represented along one dimension and innermost loop iterations along the other dimension. By exploiting the regularity along the loop dimension, and imposing essential dependence based constraints on intra-tile execution order, the problem of optimizing register pressure is cast in a constraint programming formalism. Experimental results are provided from thousands of innermost loops extracted from the SPEC benchmarks, demonstrating improvements over the current state-of-the-art.

An optimal linear-time algorithm for interprocedural register allocation in high level synthesis is presented. Historically, register allocation has been modeled as a graph coloring problem, which is nondeterministic polynomial time-complete in general; however, converting each procedure to static single assignment (SSA) form ensures a chordal interference graph, which can be colored in O(V + E) time; the interprocedural interference graph (IIG) is not guaranteed to be chordal after this transformation. An extension to SSA form is introduced which ensures that the IIG is chordal, and the conversion process does not increase its chromatic number. The resulting IIG can then be colored in linear-time.

A robust system is one that can ensure essential services in spite of faults and failures in useful but non-essential components. Unless we can ensure that critical services can only USE but not depend on less critical components, a seemingly minor fault can propagate along complex and implicit dependency chains and bring down the system. Modern real time systems are often developed concurrently by multiple teams. A team typically only knows the dependency relations between their components and neighboring components. In addition, dependency relations will change as software components and their interactions are being modified. Therefore, how to automatically track and analyze the system wide dependency from local information is important for the development of robust real time systems. This paper presents dependency algebra - a unified theoretical framework plus a prototype toolkit for dependency management in real-time systems

With the development of fabrication, the capacities of application-specific integrated circuits (ASICs) that implement data-intensive applications are increasing as well. in high-level view, the results of functional units (FUs) and register allocation have a significant impact on power, thermal, area and timing etc., especially for data-dominated behaviors. Techniques for power minimization might be applied in different levels of the design hierarchy, but high-level synthesis (HLS) has attracted a special attention due to its inherent ability of better design space exploration. All kinds of methods for register optimization are presented in the recent past. This paper presents a new simultaneous FUs and register allocation method, which combining heuristic list scheduling algorithm and left-edge algorithm to optimize register number and power. From the experimental results, it shows that different FUs allocation results deliver an average 1.83 reduction in register number. And compared with traditional allocation method, we can obtain a 5.81% reduction in power consumption. In order to optimize area with the design demand, it will be at the expense of power dissipation, our design method also can achieve power-area balance.

Relative thermal pleasure model: A unified framework for understanding and predicting thermal comfort in dynamic environments

The timetabling problem is well known to be an NP-complete combinatorial problem. The problem becomes even more complex when addressed to individual timetables of students. The core of dealing with the problem in this application is a timetable builder based on mixed direct-indirect encoding evolved by a genetic algorithm with a self-adaptation paradigm, where the parameters of the genetic algorithm are optimized during the same evolution cycle as the problem itself. The aim of this paper is to present an encoding for self-adaptation of genetic algorithms that is suitable for timetabling problems. Compared to previous approaches we designed the encoding for self-adaptation of not only one parameter or several ones but for all possible parameters of genetic algorithms at the same time. The proposed self-adaptive genetic algorithm is then applied for solving the real university timetabling problem and compared with a standard genetic algorithm. The main advantage of this approach is that it makes it possible to solve a wide range of timetabling and scheduling problems without setting parameters for each kind of problem in advance. Unlike common timetabling problems, the algorithm was applied to the problem in which each student has an individual timetable, so we also present and discuss the algorithm for optimized enrollment of students that minimizes the number of clashing constraints for students.