Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory

The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new loop scheduling with memory management technique, iterational retiming with partitioning (IRP), that can completely hide memory latencies for applications with multi-dimensional loops on architectures like CELL processor (J.A. Kahle et al., 2005). In IRP, the iteration space is first partitioned carefully. Then a two-part schedule, consisting of processor and memory parts, is produced such that the execution time of the memory part never exceeds the execution time of the processor part. These two parts are executed simultaneously and complete memory latency hiding is reached. Experiments on DSP benchmarks show that IRP consistently produces optimal solutions as well as significant improvement over previous techniques.

The need for increased memory capacity, which also needs to be affordable and sustainable, leads to the adoption of heterogeneous memory hierarchies, combining DRAM and NVM technologies. This work proposes a memory management methodology that relies on multi-objective optimization in terms of performance, energy consumption and impact on NVM’s lifetime, for applications deployed on heterogeneous (i.e., DRAM/NVM) memory systems. We propose a scalable and lightweight data structure exploration flow for supporting data type refinement based on access pattern analysis, enhanced with a weighted-based data placement decision support for multi-objective exploration and optimization. The evaluation of the methodology was performed both on emulated and real DRAM/NVM hardware for different applications and data placement algorithms. The experimental results show up to 58.7% lower execution time and 48.3% less energy consumption compared with the results obtained by the initial versions of the applications. Moreover, we observed 72.6% less NVM write operations, which can significantly extend the lifetime of the NVM memory. Finally, thorough evaluation shows that the methodology is flexible and scalable, as it can integrate different data placement algorithms and NVM technologies and requires reasonable exploration time.

In this paper, the problem of parallel loop scheduling for heterogeneous networks of workstations is discussed. A practical network of workstations is heterogeneous where computing power varies in different composing workstations. A simple loop scheduling technique is insufficient in exploiting maximum computing power of such a system. We propose a fundamental idea for a performance prediction tool to gauge the relative computing power among composing workstations so that parallel performance of a program run on a given network can be predicted. In view of the performance prediction results, a loop scheduling approach is then incorporated into the system to achieve close-to-optimal parallel performance. Examples running benchmark programs demonstrate a significant gain from the proposed approach over traditional scheduling approaches.

This paper uses timed Petri net to model and analyze the problem of instruction-level loop scheduling with resource constraints, which has been proven to be an NP complete problem. First, we present a new timed Petri net model to integrate functional unit allocation, register allocation and spilling into a unified theoretical framework. Then we develop a state subgraph, called Register Allocation Solution Graph, which can effectively describe the major behavior of our new model. The main property of this state subgraph is that the number of all its nodes is polynomial. finally we present and prove that the optimum loop schedules can be found with polynomial computation complexity, for almost all practical loop programs. Our work lightens a new idea of finding the optimum loop schedules.

DRAM technology faces density and power challenges to increase capacity because of limitations of physical cell design. To overcome these limitations, system designers are exploring alternative solutions that combine DRAM and emerging NVRAM technologies. Previous work on heterogeneous memories focuses, mainly, on two system designs: PCache, a hierarchical, inclusive memory system, and HRank, a flat, non-inclusive memory system. We demonstrate that neither of these designs can universally achieve high performance and energy efficiency across a suite of HPC workloads. In this work, we investigate the impact of a number of multi-level memory designs on the performance, power, and energy consumption of applications. To achieve this goal and overcome the limited number of available tools to study heterogeneous memories, we created HMsim, an infrastructure that enables n-level, heterogeneous memory studies by leveraging existing memory simulators. We, then, propose HpMC, a new memory controller design that combines the best aspects of existing management policies to improve performance and energy. Our energy-aware memory management system dynamically switches between PCache and HRank based on the temporal locality of applications. Our results show that HpMC reduces energy consumption from 13% to 45% compared to PCache and HRank, while providing the same bandwidth and higher capacity than a conventional DRAM system.

In this paper, we develop a novel real-time instruction-level loop scheduling technique to reduce leakage energy consumption for applications with loops on VLIW architecture. We first prove that the scheduling problem with the minimum leakage energy consumption within a timing constraint is NP-complete. Then, LEMLS (leakage energy minimization loop scheduling) algorithm is designed to repeatedly regroup a loop based on rotation scheduling (Chao et al., 1997), and decrease leakage energy integrating with leakage power reduction mechanism. We conduct experiments on a set of DSP benchmarks based on the power model of the VLIW processors in (Liao et al., 2002). The results show that our algorithm achieves significant leakage energy saving compared with list scheduling and the algorithm in (You et al., 2006).

Energy efficient design for hardware and software implementations plays an important role in pivoting the system towards reliability without any considerable limitations. Energy consumption is a critical design issue in real time system. The main challenge in battery operated system is maintaining high performance. Dynamic voltage scaling and dynamic frequency scaling is used to adjust supply voltage and processor frequency to adapt the workload demand for better energy management. From the literature survey, the problem of local optima, resources constraints, task assignment and scheduling are identified for energy management. To solve these problems, local with restarts algorithm (LSR) and voltage assignment algorithms (PVAP) are proposed to address the problem of Processor and Voltage Assignment with Probability by adopting a probabilistic approach of tasks in real-time embedded systems. A task DAG (Directed Acyclic Graph) is used to model the PVAP problem. In order to facilitate dynamic voltage scaling, voltage assignment algorithm is worked out with execution time and energy units as considerations and it encounters a common node problem. As an effective aid local search with restarts algorithm is used this proves effective against local optima too. The experiment has been done on different benchmark sets.

The method of Cost Oriented Competing Processes (COCP) is a new approach to handle assignment problems and combinatorial optimization problems. The COCP method works with a system of nonlinear coupled ordinary differential equations with suitable stable points. In contrast to many other techniques, this method can easily be generalized and adapted to different assignment problems, even to those of higher order and with additional constraints. In assignment problems of higher order, the single costs which have to be considered for the total costs depend on several decisions instead of only one decision as in linear assignment problems. The handling of those higher order assignment problems is important for several scheduling problems such as manufacturing planning and time table planning.

Most research to date on energy minimization in DSP processors has focuses on hardware solution. This paper examines the software-based factors affecting performance and energy consumption for architecture-aware compilation. We focus on providing support for one architectural feature of DSPs that makes code generation difficult, namely the use of multiple data memory banks. This feature increases the memory bandwidth by permitting multiple data memory accesses to occur in parallel when the referenced variables belong to different data memory banks and the registers involved conform to a strict set of conditions. We present novel instruction scheduling, register and memory allocation algorithms that attempt to maximize the performance, minimize the energy, and therefore, maximize the benefit of this architectural feature. Experimental results demonstrate that our algorithms generate high performance, low energy codes for the DSP architectural features with multiple data memory banks. Our algorithm led to improvements in performance and energy consumption of 48.3% and 66.6% respectively in our benchmark examples.

This paper describes a new method for modeling and solving different scheduling and resource assignment problems that are common in high-level synthesis (HLS) and system-level synthesis. It addresses assignment of resources for operations and tasks as well as their static, off-line scheduling. Different heterogeneous constraints are considered for these problems. These constraints can be grouped into two classes: problem-specific constraints and design-oriented constraints. They are uniformly modeled, in our approach, by finite domain (FD) constraints and solved using related constrained programming (CP) techniques. This provides a way to improve quality of final solutions. We have developed in Java a constraint solver engine, JaCoP ( Ja va Co nstraint P rogramming), to evaluate this approach. This solver and a related framework make it possible to model different resource assignment and scheduling problems, and handle them uniformly. The JaCoP prototype system has been extensively evaluated on a number of HLS and system-level synthesis benchmarks. We have been able to obtain optimal results together with related proofs of optimality for all HLS scheduling benchmarks and for all explored design styles (except one functional pipeline design). Many system-level benchmarks can also be solved optimally. For large randomly generated task graphs, we have used heuristic search methods and obtained results that are 1--3% worse than lower bounds or optimal results. These experiments have proved the feasibility of the presented approach.

The aim of this paper is to present a branch and bound approach to solve a k-stage hybrid flowshop scheduling problem in order to minimize the total completion time. This scheduling problem encloses three subproblems: lot sizing, scheduling and assignment problems. In this paper only scheduling and assignment are taken into account because we suppose that the lot sizing problem has already been solved. The method we propose is an optimal method, based on a special architecture of search tree which allows us to solve the two subproblems considered. Some lower bounds are proposed. Then computational results are given and proved that results are acceptable. Finally, two theorems demonstrate some dominance relations.

Dynamic Voltage Scaling (DVS) is one of the techniques used to obtain energy-saving in real-time DSP systems. In many DSP systems, some tasks contain conditional instructions that have different execution times for different inputs. Due to the uncertainties in execution time of these tasks, this paper models each varied execution time as a probabilistic random variable and solves the Voltage Assignment with Probability (VAP) Problem. VAP problem involves finding a voltage level to be used for each node of an date flow graph (DFG) in uniprocessor and multiprocessor DSP systems. This paper proposes two optimal algorithms, one for uniprocessor and one for multiprocessor DSP systems, to minimize the expected total energy consumption while satisfying the timing constraint with a guaranteed confidence probability. The experimental results show that our approach achieves significant energy saving than previous work. For example, our algorithm for multiprocessor achieves an average improvement of 56.1% on total energy-saving with 0.80 probability satisfying timing constraint.

Effective project management implies the use of advanced planning and scheduling methods that allow to determine feasible sequences of activities and to complete a project on time and on budget. Traditional scheduling tools like fundamental Critical Path Method (CPM) and various methods for Resource Constrained Project Scheduling Problem (RCPSP) and Time Constrained Project Scheduling Problem (TCPSP) have many shortcomings for construction projects where spatial factor plays a critically important role. Previous attempts to interpret space as a specific resource were successful for particular problems of line-of-balance scheduling, space scheduling, dynamic layout planning, horizontal and vertical logic scheduling, workspace congestion mitigating, scheduling multiple projects with movable resources, spatial scheduling of repeated and grouped activities and motion planning. However, none of these methods considers the spatio-temporal requirements in a holistic framework of generic RCPSP problem and provides feasible results accounting for workspace and workflow factors. In this paper we start with the classical RCPSP statement and then present mathematically strong formalisation of the extended generalised problem, taking into account workspace congestion and workflow disturbance constraints specified in practically meaningful and computationally constructive ways. For the generalised RCPSP problem an effective scheduling method is proposed. The method tends to minimise the project makespan while satisfying timing constraints and precedence relations, not exceeding resource utilisation limits, avoiding workspace congestions and keeping workflows continuous. The method reuses so-called serial scheduling scheme and provides for additional computational routines and heuristic priority rules to generate feasible schedules satisfying all the imposed requirements. Advantages of the method and prospects for its application to industrial needs are outlined in the paper too.

Effective project management implies the use of advanced planning and scheduling methods that allow to determine the feasible sequences of activities and to complete a project on time and on budget. Traditional scheduling tools like fundamental Critical Path Method (CPM) and various methods for Resource Constrained Project Scheduling Problem (RCPSP) and Time Constrained Project Scheduling Problem (TCPSP) have many shortcomings for the construction projects where spatial factor plays critically important role. Previously taken attempts to interpret space as a specific resource were successful for particular problems of line-of-balance scheduling, space scheduling, dynamic layout planning, horizontal and vertical logic scheduling, workspace congestion mitigating, scheduling multiple projects with movable resources, spatial scheduling of repeated and grouped activities, motion planning. However, none of these methods considers the spatio-temporal requirements in a holistic framework of generic RCPSP problem and provides feasible results accounting for workspace and workflow factors. In the paper we start with the classical RCPSP statement and then present mathematically strong formalization of the extended generalized problem taking into account workspace congestion and workflow disturbance constraints specified in practically meaningful and computationally constructive ways. For the generalized RCPSP problem an effective scheduling method is proposed. The method tends to minimize the project makespan while satisfying timing constraints and precedence relations, not exceeding resource utilization limits, avoiding workspace congestion and keeping workflows continuous. The method reuses so-called serial scheduling scheme and provides for additional computational routines and heuristic priority rules to generate feasible schedules satisfying all the imposed requirements. In order to evaluate the method, benchmark sets are proposed and investigated. Advantages of the method and prospects for its application to industrial needs are outlined in the paper too.

The 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> generation Intel® Xeon Phi processor (codenamed Knights Landing) is Intel's first self-booting Xeon Phi processor that is aimed at the HPC market. Like its predecessor, KNL is a many-core, highly threaded processor featuring an innovative on-die mesh interconnect and an on-package high bandwidth memory MCDRAM in addition to DRAM DDR-2400, which makes it possible for many HPC applications to achieve much higher performance by leveraging heterogeneous memory configuration. In this paper, we look at the programming challenges for software developers to create and manipulate data using different memory modes and a heap management API to satisfy the ever-increasing demand for high bandwidth and low latency. We start with a functional KNL architecture introduction with an emphasis on the memory subsystem and memory usage model, followed by the utility tools required to run the applications under various scenarios. We then present a profiler-based heterogeneous memory optimization framework for all memory-bandwidth-intensive applications. The new memory object features in Intel® VTune™ Amplifier will be introduced and discussed. Finally, we show how to leverage different kinds of memory by using a user extensible memory heap management API also known as memkind API. Throughout our discussions, we will use a classic streaming application in quantitative finance, the Black-Scholes benchmark. We show how to highlight the memory bottleneck using the new memory profiling features in the Intel VTune Amplifier and how to achieve high bandwidth by removing the bottleneck and by allocating memory threads between different types of memory. In the end, we show the peak performance we can achieve on KNL by using a combination of MCDRAM and DDR.