Using transition fault test patterns for cost effective offline performance estimation

Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologies are not sufficient to test the retention flip-flop thoroughly. This paper presents four new fault models and the testing of retention flip-flop. The four fault models are awake-mode stuck-at fault, sleep-mode stuck-at fault, awake-mode transition fault, and sleep-mode transition fault. The four faults model the defects that affect the retained value, wakeup time, and sleep time of retention flip-flops. Based on the new fault models, test patterns for retention flip-flop can be easily generated by current automatic test pattern generation tools. The proposed test methodology is validated by performing experiments on ISCAS'89 benchmark circuits and some realistic industrial low power designs. The experimental results show that the faults of retention flip-flops can be easily detected by our method and the average fault coverage is higher than 98%. The fault coverage of conventional single stuck-at fault and transition fault test can be increased by more than 1%.

A study is presented concerning the efficiency of test pattern sets generated with the transition fault model applied to fine grained delay fault models. The authors have developed the delay fault simulator DELFI-a program which is capable of simulating timing failures of combinational circuits using different delay fault models. For the computer experiments the authors selected transition fault test pattern sets because they are very cost-effective to generate. The simulations of benchmark circuits demonstrate that the transition fault test patterns detect gross delay faults even at nodes with redundant stuck-at faults. Furthermore the results show that the transition fault test patterns are not sufficient for small delay faults in the range of a few gate delays. In order to receive a satisfactory coverage for these delay faults, the transition fault test sets must be extended. >

This paper presents a novel test pattern generation flow to detect stuck-at and transition faults simultaneously. Both fault models are transformed into a unified fault model for a proposed 2-time-frame circuit model. This makes it possible to generate patterns for both types of faults in one ATPG run with no need to modify the ATPG tool. A highly compact pattern set can thus be obtained which requires less test data volume and shorter test application time without degrading the fault coverage for either type of faults. Experimental results show that, compared to the conventional methods, the proposed method can reduce the total test pattern counts by up to 12.27% and 15.54% and test application times up to 12.06% and 15.58% for ISCAS'89 and ITC'99 circuits, respectively.

Test generation procedures target a variety of fault models in order to produce test sets that are effective for defect detection. This paper considers the likely scenario where two-cycle skewed-load tests are generated to detect single transition faults, and the test set is complemented with tests for single stuck-at faults that are not detected by the transition fault test set. For this scenario, this paper makes several unique observations that can be utilized to produce a single compact test set that consists only of two-cycle skewed-load tests for both fault models. The first observation is that a single-cycle test for a stuck-at fault can be transformed into a skewed-load test that is guaranteed to detect the stuck-at fault without performing logic or fault simulation. The second observation is that skewed-load tests, which are transformed from single-cycle tests for stuck-at faults, sometimes detect more transition and stuck-at faults than tests that were generated for transition faults. The third observation is that a static test compaction procedure, which is based on the modification and removal of tests, is effective in this context because it allows tests for stuck-at faults to detect more transition faults and vice versa. This paper describes a test compaction procedure based on these observations and presents experimental results for benchmark circuits to demonstrate the effectiveness of the procedure.

The use of both broadside (launch-on-capture) and skewed-load (launch-on-shift) tests for delay faults results in increased delay fault coverage and better test compaction than the use of a single test type. Two-cycle broadside and skewed-load tests differ in the sequence of length two applied to the scan-enable input between the scan-in and scan-out operations of a test. Considering a circuit with a single clock domain, the question that this article attempts to answer is whether it is possible to generate a complete test set for transition faults where all the tests use the same scan-enable sequence of length three or more. The use of a single scan-enable sequence simplifies the test application process. Experimental results demonstrate that there is a significant number of benchmark circuits for which a test set with a single scan-enable sequence achieves the same transition fault coverage as a test set that consists of both broadside and skewed-load tests. For other benchmark circuits, a small loss in transition fault coverage compared with the use of both test types allows a single scan-enable sequence to be used.

Peak power consumption during test for the low power devices is a major concern [2, 3, 4]. Excessive peak power may result in test failures of functionally good devices. Huge peaks in the instantaneous power consumption will result in high rates of change of current (di/dt) causing adverse noise effects like VDD-drop and ground-bounce [1, 2, 3, 4]. Also, a high frequency of occurrence of high di/dt may cause severe decrease in the reliability of the circuit [1]. Hence the process of testing low power devices must be peak power aware. This paper provides a method to minimize the peak power during speed capture phase by partitioning the nodes into two zones based on their timing slacks. One of the zones contains the timing-critical nodes, while the other contains the non timing-critical ones. Each zone may be split into multiple bins. Test patterns are generated independently for each bin, targeting the nodes belonging to that bin alone, thus reducing the size of the target set. It is very important that the peak power consumed by the test patterns for each bin in the timing-critical zone is well within the tolerable limit. The bins in the non timing-critical zone may be allowed to have peak power consumptions very close to the limit or even marginally higher because the large positive slacks on these nodes will make up for the extra delay through the cells caused by VDD-drop/ground-bounce. This approach allows the designer to have a better control over each pattern and also helps to minimize the effects of high peak power and high di/dt.

In enhanced-scan circuits, a two-pattern test < t i , t j > for a transition fault can be obtained by using a test t j that detects a stuck-at fault, and preceding it by a test t i that activates another stuck-at fault. Thus, test generation for transition faults can be done by combining pairs of stuck-at tests. This provides an alternative to deterministic test generation, as well as reduces the test storage requirements for transition fault tests. We study the possibility of generating scan-based tests for transition faults in standard-scan circuits in a similar way, by combining pairs of stuck-at tests. Since it is not always possible to obtain a standard-scan test that is equivalent to a two-pattern test < t i , t j > based on stuck-at tests t i and t j , it is not always possible to guarantee that the combination of t i and t j will detect a transition fault. To compensate for this, it is necessary to try combinations of different stuck-at test pairs, resulting in an increased simulation effort to compute effective standard-scan tests. Our focus in this work is on reducing this simulation effort by reducing the number of stuck-at test pairs that need to be considered.

To distinguish between a pair of transition faults, we need to find a test vector pair (LOC or LOS type)that produces different output responses for the two faults. By adding a few logic gates and one modeling flip-flop to the circuit under test (CUT), we create a diagnostic ATPG model usable by a conventional single stuck-at fault test pattern generator. Given a transition fault pair, this ATPG model either finds a distinguishing test or proves the faults to be equivalent. An efficient diagnostic fault simulator is devised to find undistinguishable fault pairs from a fault list by a test vector set. The number of fault pairs that needs to be targeted by the ATPG is greatly reduced after diagnostic fault simulation. We use a previously proposed diagnostic coverage (DC) metric to determine the distinguishability (diagnosability) of a test vector set. Experimental results show improved DC for benchmark circuits after applying the proposed diagnostic ATPG algorithms.

As fabricated circuitry becomes larger and denser, the modern industrial automatic test pattern generation techniques, which focus on the detection of single faults, become more likely to overlook multiple (simultaneous) faults. Although there are exponentially more multiple faults than single faults in any given circuit design, only a few additional test patterns are needed to cover all of the multiple faults, if the test generation starts from the complete test set for single faults. In this paper, we first show the case where test patterns for single faults are sufficient to cover all multiple faults, and then explain in which conditions some of the multiple faults may be overlooked. Based on this analysis, we propose a method that can efficiently generate the complete test set for double faults without traversing all the faults. Since most of the double faults can be detected by the single faults' test set, the proposed method only selects the uncovered double faults by analyzing the propagation paths of single faults, and then generating new test patterns only for those uncovered faults. The experimental results show that based on the single faults' test set, the proposed method only needs to create a small number of additional test patterns to cover all double faults in most of the given circuits. By repeating the same process, the proposed method can be incrementally applied to deal with all multiple faults.

A technique for modifying networks so that they are capable of self test is presented. The major innovation is partitioning the network into subnetworks with sufficiently few inputs that exhaustive testing of the subnetworks is possible. Procedures for reconfiguring the existing registers into modified linear feedback shift registers (LFSR's) which apply the exhaustive (not pseudorandom) test patterns or convert the responses into signatures are described. No fault models or test pattern generation programs are required. A method to modify CMOS circuits so that exhaustive testing can be used even when stuck-open faults must be detected is described. A detailed example using the 74181 ALU is presented.

A FAST fault model is proposed for small delay faults induced by cross-gate defects in FinFET. FAST ATPG, fault simulation, and test selection are presented to generate and select test patterns to detect FAST faults. Experiments on large benchmark circuits show that our pattern sets have approximately 29% and 4% better FAST coverage and FAST SDQL respectively than those of commercial tool timing-unaware 1-detect pattern sets.

Accuracy of any diagnosis algorithm depends on the test set used. Test that is able to distinguish more fault pairs is better suited for aiding diagnosis. Standard detection test set is generated to detect faults using less number of test patterns. It is unable to distinguish many fault pairs. To distinguish pairs, more patterns are required that consumes ATE memory and time. In this work we devised an algorithm to generate tests from the detection test itself. The generated tests distinguish transition fault pairs undistinguished by the detection test. Our distinguishing tests are made from the detection test by rearrangement of pseudo-primary and primary input of the two-pattern tests. Additional tester memory is not required for our diagnostic tests.

A new and effective pseudorandom test pattern generator, termed GLFSR, is introduced. The test pattern generation by GLFSR achieves a higher degree of randomness. Experimental results on common benchmark CUT demonstrate that the fault coverage of the propose pattern generator is significantly higher compared to conventional pattern generation techniques. For Cutpsilas stuck-at fault and transition faults, test pattern generator using GLFSR can attain equivalent fault coverage but fewer patterns than LFSR pattern generator. GLFSR can be used as test pattern for the architecture of BIST.

As a method to evaluate delay test quality of test patterns, SDQM (Statistical Delay Quality Model) has been proposed for transition faults. In order to derive better test quality by SDQM, the following two things are important: for each transition fault, (1) to find out the accurate length of the longest sensitizable paths along which the fault is activated and propagated, and (2) to generate a test pattern that detects the fault through as long paths as possible. In this paper, we propose a method to calculate the length of the potentially sensitizable longest path for detection of a transition fault. In addition, we develop a procedure to extract path information that helps high quality transition ATPG. Experimental results show that the proposed method improves SDQL (Statistical Delay Quality Level) by not only accurate calculation of the longest sensitizable paths but also detection of faults through longer paths.

The paper shows how to generate a function that contains all possible tests to detect a transition fault. Moreover, a systematic methodology is presented that derives the functions for all transition faults based on only two circuit traversals. Quality tests are generated by requiring that the function formulation considers established sensitization criteria to either activate a transition at the fault site or propagate it to a circuit output. Experimental results on the ISCAS'85 and ISCAS'89 benchmarks demonstrate the promise of the method which can also lead to efficient compaction methods for transition faults.