Variability in Multistage Synchronizers

International audience

Exploring XOR-based Full Adders and decoupling cells to variability mitigation at FinFET technology

Analog behavioral equivalence boundary computation under the effect of process variations

Near threshold computing (NTC) has significant role in reducing the energy consumption of modern very large scale integrated circuits designs. However, NTC designs suffer from functional failures and performance loss. Understanding the characteristics of the functional failures and variability effects is of decisive importance in order to mitigate them, and get the utmost NTC benefits. This paper presents a comprehensive cross-layer reliability analysis framework to assess the effect of soft error, aging, and process variation in the operation of near threshold voltage caches. The objective is to quantify the reliability of different SRAM designs, evaluate voltage scaling potential of caches, and to find a reliability-performance optimal cache organization for an NTC microprocessor. In this paper, the soft error rate (SER) and static noise margin (SNM) of 6T and 8T SRAM cells and their dependencies on aging and process variation are investigated by considering device, circuit, and architecture level analysis. Their experimental results show that in NTC, process variation and aging-induced SNM degradation is $2.5{\boldsymbol \times }$ higher than in the super threshold domain while SER is $8{\boldsymbol \times }$ higher. At NTC, the use of 8T instead of 6T SRAM cells can reduce the system-level SNM and SER by 14% and 22%, respectively. Besides, we observe that we can find the right balance between performance and reliability by using an appropriate cache organization at NTC which is different from the super threshold.

Winner-Take- All (WTA) circuit chooses a winner input from a set of input signals. WTA circuits employ transistors that operate in the sub-threshold or weak inversion region. With technology scaling, sub-threshold circuits are prone to mismatch and process variations which degrade the performance of these circuits. This paper presents a novel WTA circuit that employs a CMOS double pair transistor as a translinear element that is more tolerant to mismatch and process variations. Monte Carlo simulations are used to compare the performance of the existing and the proposed topologies to estimate the effects of process and mismatch variations. Results show that the proposed circuit is able to reduce the range of variations by three orders of magnitude compared to original one for similar variations in the transistor parameters. The proposed element also shows better accuracy in replicating the maximum input current compared to the original circuit.

Effect of material and process variability on the formability of aluminium alloys

The present work focused specifically on two fabrication processing methods, namely, vacuum-assisted resin transfer moulding (VARTM) and double vacuum-assisted resin transfer moulding (DVARTM) processing methods. DVARTM was essentially a modified VARTM process. The research focused on the effect of nanoparticle dispersion within the composite and the effect of process variation on its mechanical properties. The resultant composites consisted of E-glass fibre (GF) infused with an epoxy matrix doped with 0, 0.1, 0.3 and 0.5 wt% of pristine multi-walled carbon nanotubes (MWCNT). Dynamic mechanical analysis (DMA), tensile testing and a quantitative “burn-out” test analysis were conducted to show the effect of MWCNT dispersion due to the process variation. The overall graphical DMA analysis for the DVARTM method revealed trends consistent to specimens containing homogeneously dispersed nanoparticle content. At 30°C, the 0.5 wt% composite from the DVARTM method displayed a 34% stiffness increase compared to VARTM with the similar wt%. Glass transition temperatures (Tg), displayed a steady incremental increase in DVARTM from 0.1 to 0.5 wt% content. The VARTM method showed a steady increase in Tg for 0.1 and 0.5 wt% content with a decline in 0.3 wt% content. In the DVARTM method, the damping for 0.1 wt% decreased by 14.5% and 10%, compared to the 0.5 wt% and the control, respectively. The decreased damping indicated an enhancement to the fillermatrix interfacial bonding. The ultimate tensile strength (UTS) had a uniform increase with increasing weight percentages of MWCNT content for the VARTM method. Both methods experienced optimum UTS with 0.3 wt% MWCNT content. A “burn-out” test on various layers of the composite along the lengths and thickness directions was conducted for both methods. The resultant quantitative analysis of the residue on the GF after combustion suggested improved dispersion of MWCNTS for the DVARTM method in comparison to VARTM. The important finding in this study highlighted that enhancements to mechanical properties were achievable when using pristine MWCNTs along with process variation, as opposed to past studies which stated that pristine MWCNTs were non-effective unless functionalized.

The esary proschan (EP) method and other approximations, based on minimal cut sets (MCSs) calculation, are commonly used in reliability system analysis. However, it is time consuming and even impossible to calculate all MCSs of large systems. Cut off by order or by probability is applied to find the most important MCSs. In this paper we discuss the efficiency and accuracy of this approach by comparing results of calculations, obtained for large industrial benchmarks using both EP and pivotal decomposition method (DM). DM (and similar binary decision diagram method) allows obtaining exact solutions for large fault trees, but it is still time consuming. We have shown that for large fault trees it is efficient to apply approximate DM in combination with truncation approach. We suggest an algorithm, which is mathematically sound and accurate enough in the entire range of probability. It is also applied efficiently in the calculation of different system parameters, such as: total downtime, frequency, expected number of failures, and mean time to failure (MTTF). The efficiency and accuracy of the approach is demonstrated by numerous calculations of complex industrial benchmarks.

In deep sub-micron technologies, the increasing effect of process and environmental variations has lead chip manufacturers to use adaptive voltage scaling techniques in order to adapt operation parameters exclusively to each chip. The increasing effect of process variation is limiting the effectiveness of current chip monitoring approaches, such as on-chip performance monitor boxes (PMBs), which results in yield loss and high design margins, thus high power consumption. This paper proposes an alternative solution for adaptive voltage scaling using delay test patterns, which is able to eliminate the need for PMBs, and thus the long expensive characterization phase of tuning PMBs to each design, while improving the yield as well as power optimization. Results show, using an industrial grade 28nm FD-SOI library developed for low power devices, that delay testing for performance prediction reduces the inaccuracy down to 1.85%.

We consider a design of quasicyclic LDPC codes which have irregular column weights. We derive bit-oriented bound and parity-oriented bound on the minimum distances of irregular quasicyclic codes using a similar technique to Tanner's simple lower bound

The high integration capacity of digital circuits, which occurs due to technological scaling, presents new challenges for nanotechnology designs. The evolution of integrated circuits has made them more susceptible to faults, besides increasing the process variability, which can lead to circuits operating outside their specification ranges. This work evaluates the effects of process variability and radiation faults on complex gates. These effects are compared to alternative circuits that implement the same functions but exploring a multi-level of basic cells as NAND2, NOR2 and Inverters. The technology adopted is 7nm FinFET ASAP. Results show that although complex cells present better timing and power results, multi-level circuits are up to 28% less sensible to radiation faults and about 40% more stable under process variability.

Modern digital systems become more complex with increasing multi-clocking techniques for better performance. Multiple asynchronous clock domains have been using for different I/O interface in today's modern system on chip (SoC). Each system needs to communicate with one or other system/peripherals continuously. These multiple asynchronous clock domains are facing meta-stability, data losses and other clock domain crossing (CDC) issues. CDC is an important issue in all today's SoC. To overcome the clock domain crossing(CDC) issues such as meta-stability and data losses, basic two flip-flop synchronizer has been designed whose performance is depends on pulse width of transmitting signal across the different clock domains, which has to be greater than 1.5X the receiver domain clock width. In this paper a short pulse synchronizer has been designed and demonstrated for variable pulse width, whose performance is independent on pulse width of the signal which transmits across the domains.

Colonization–competition trade‐offs represent a stabilizing mechanism that is thought to maintain diversity of forest trees. If so, then early‐successional species should benefit from high capacity to colonize new sites, and late‐successional species should be good competitors. Tests of this hypothesis in forests have been precluded by an inability to estimate the many factors that contribute to seed production and dispersal, particularly the many types of stochasticity that contribute to fecundity data. We develop a hierarchical Bayes modeling structure, and we use it to estimate fecundity schedules from the two types of data that ecologists typically collect, including seed‐trap counts and observations of tree status. The posterior density is obtained using Markov‐chain Monte Carlo techniques. The flexible structure yields estimates of size and covariate effects on seed production, variability associated with population heterogeneity, and interannual stochasticity (variability and serial autocorrelation), sex ratio, and dispersal. It admits the errors in data associated with the ability to accurately recognize tree status and process misspecification. We estimate year‐by‐year seed‐production rates for all individuals in each of nine sample stands from two regions and up to 11 years. A rich characterization of differences among species and relationships among individuals allows evaluation of a number of hypotheses related to masting, effective population sizes, and location and covariate effects. It demonstrates large bias in previous methods. We focus on implications for colonization–competition and a related hypothesis, the successional niche—trade‐offs in the capacity to exploit high resource availability in early successional environments vs. the capacity to survive low‐resource conditions late in succession.Contrary to predictions of trade‐off hypotheses, we find no relationship between successional status and fecundity, dispersal, or expected arrivals at distant sites. Results suggest a mechanism for maintenance of diversity that may be more general than colonization– competition and successional niches. High variability and strong individual effects (variability within populations) generate massive stochasticity in recruitment that, when combined with “storage,” may provide a stabilizing mechanism. The storage effect stabilizes diversity when species differences ensure that responses to stochasticity are not highly correlated among species. Process variability and individual effects mean that many species have the advantage at different times and places even in the absence of “deterministic” trade‐offs. Not only does colonization vary among species, but also individual behavior is highly stochastic and weakly correlated among members of the same population. Although these factors are the dominant sources of variability in data sets (substantially larger than the deterministic relationships typically examined), they have not been not included in the models that ecologists have used to evaluate mechanisms of species coexistence (e.g., even individual‐based models lack random individual effects). Recognition of the mechanisms of coexistence requires not only heuristic models that capture the principal sources of stochasticity, but also data‐modeling techniques that allow for their estimation.

Critical transistors nexus based circuit-level aging assessment and prediction

Process variations can have a significant impact on both device and interconnect performance in deep sub-micron (DSM) technology. In this paper, initially authors discuss the effects of process parameter variations on bus-encoding schemes for delay minimization in VLSI interconnects. Later, process variation aware bus-coding scheme is proposed to reduce delay in interconnects. It is shown that if process variability is taken into consideration, effective capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ) of the bus lines varies because of which the amount of delay that each crosstalk class causes is going to vary. SPICE simulations have been carried out for interconnect lines of different dimensions at different technology nodes (180, 130, 90 and 65 nm) to find out the effect of process variation on the effective capacitance of bus lines and to evaluate the percentage delay reduction due to proposed coding scheme.