Via design rule consideration in multilayer maze routing algorithms

Design automation for analog and mixed signal designs has become more important, as analog and digital components are integrated on the same system-on-chips (SOCs). Exact route matching is an important constraint for analog and mixed signal designs with non-uniform metal stacks. In this paper, we propose a constrained-path based maze routing algorithm that can handle exact matching constraints for multiple nets. We also propose a scalable framework that utilizes the proposed maze routing algorithm for realistic problem sizes. Compared to the pattern routing algorithms proposed recently [8], our algorithms allow a more thorough exploration of the solution space by allowing bends to be inserted to avoid congested regions. The experimental study demonstrates that the proposed algorithm leads to significant reductions in congestion costs compared to the previous algorithm.

Feasibility study of the application of voltage contrast to printed circuit board

A Novel Architectural Framework for 2-D Global Routing Using Hybrid Biogeography-Based Optimization and Maze Routing Algorithm

Lee's maze routing algorithm is parallelized and implemented on an Intel iPSC/2 hypercube multicomputer. Our contribution to the previous work in [2] is that we propose a new parallel front wave expansion scheme which performs two front wave expansions concurrently, one starting from the source cell and the other one starting from the target cell. The proposed scheme increases the processor utilization and decreases the total number of interprocessor communications. We experimentally show that our scheme outperforms the scheme given in [2]

Since the 1960s, interconnection technology has been dominated by implementations of printed circuit board (PCB) technology. However, in response to the ever increasing demand for higher routing densities and improved electrical performance, this technology has been increasingly challenged by multichip module (MCM) technology and in particular the MCM‐L type. MCM‐L technology is a laminate construction and is basically a further development of PCB technology with two or more bare chips and fine line interconnects. Consequently, it is perceived that the current PCB fabricators are ideally positioned to take the initiative with MCM‐L technology. Reviews the current state of PCB industry and MCM‐L technological (process and material) requirements, within the UK, such that a comparison can be made between the two technologies. Planning, training and investment requirements for new technology implementation are then identified and compared with PCB fabricators’ technological, training, planning and investment capabilities. The shortfalls between MCM‐L fabrication requirements and PCB fabricators capability are identified and discussed.

Decreasing the bill of materials for an electronic device saves development time, money and space. The integration of more and more functions not only on the chip (SoC; system on chip) but also in the package (SiP; system in package) is therefore a natural and very important step in the devolvement of micro electronics. Realizing the goal of Ambient Intelligence requires low cost system solutions where all necessary components are integrated. The future will be a combination of “System on Chip”- and “System in Package” solution called as “Heterogeneous Integration”. As far as technical and economical feasible “System on Chip” solutions will be chosen, the adoption to various applications and the integration of highly complex systems containing non-electronic functions will be carried out more cost efficiently, with a high degree of miniaturization and flexibility in “Heterogeneous Integration”. “Heterogeneous Integration” integrates several chips or components in one package (system in package or SiP) and carries out the interface to the application environment. This paper will summarize a variety of heterogeneous integration technologies researched at Fraunhofer IZM with a strong focus on embedding in printed circuit boards and embedding in molded reconfigured wafers – looking also on the requirements of sensor packaging. Not only the technological principles but also specific material demands and necessary processes as 3D routing and also 3D interconnection will be discussed in detail. Application examples and technology demonstrators from will be shown to demonstrate technological potential and challenges of miniaturized heterogeneous integration by embedding from a European perspective.

Heterogeneous integration for system in package (SiP), flip-chip integration in 3D packaging and embedded ICs in advanced Printed Circuit Boards (PCB) are all pushing the limits for low profile packaging. Advanced polymer materials applied in Semiconductor-on-Polymer™ wafer level chip scale packaging (SoP WLCSP) are gaining traction as a high reliability ultra-thin packaging solution. The 2019 roadmap for Heterogeneous Integration defines heterogeneous Integration (HI) as the integration of separately manufactured components into a higher-level assembly that provides enhanced functionality and improved operating characteristics. The development of this technology is a significant industry challenge that can evolve quickly with the application of SoP polymer based packaging. At advanced nodes, die yield falls exponentially with die size. Splitting a large monolithic SoC into smaller tightly coupled die, is an attractive alternative considering that die cost per unit area is escalating. The smartphone industry has been an early adopter of HI technologies in the use of SiP for multiple generations, essentially for the advantages in miniaturization, modularity for co-design, and enhanced generation-over-generation performance. The application processor is almost always on the most advanced node and housed in a Package on Package (PoP) configuration with memory component(s) stacked on top of this ASIC. Teardowns of the Package-on-Package (PoP) packages for Apple XSMax, Samsung Galaxy S9+, and Huawei 20 Pro have shown the utilization and need for continued z-axis thickness scaling. Implementation of SoP CSP for package in package integration or for chip on thin PCB, interposer or flex can provide another package capability for evolution of multi-layer heterogeneous integration. Reliable ultra-thin polymerized die have the potential to tackle the third dimension (z-axis) of total IC package volume in 3D integration. SoP die can replace current full thickness or partially thinned (typically >250µm) die with <35µm package thickness devices. In addition, the SoP process has the potential to extend package roadmaps enabling smaller higher performance packages in several areas, including Fan-Out (FO). Thin bridge die could simplify localized high IO for substrates. Thin embedded IPD (integrated passive devices) have the potential to increase the capability and shrink the size of substrate process based passives, similar to the performance increase for wafer based devices versus printed electronics. In addition thin high IO die could allow simplified embedding in substrates. The differentiation of PCBs, interposers and flex circuits is starting to blur. Package integration within the layers of these devices can create embedded ICs that take less system space and improve system performance. Traditionally, manufacturing steps to place an IC within the board substrate vary and require space to be created for the component body, in the form of a cavity for traditional packaged ICs. In Integrated module board (IMB), components are aligned and placed inside a cavity that is routed to the core laminate by controlled-depth routing. The cavity is filled with molding polymer to ensure chemical, mechanical, and electrical compatibility with the substrate. Isotropic solder is impregnated with the polymer to form reliable solder joints when the embedded part is laminated into the stack. Polymerized ICs in SoP CSP eliminate cavity requirements and molding polymers for IMB. Chip in polymer (CIP) approaches use thin chips in built up dielectric layers of PCBs, rather than integrating them into the core layers. When SoP CSP is applied, it is feasible to achieve the same capability, but with a much smaller z-axis and without creating a surface geography perturbation. This presentation will include an introduction to SoP CSP utilizing advanced polymer technology for accelerating evolution of HI, PoP and Embedded applications.

For an ATM switch system, we have developed a 100-Gb/s input/output (I/O) throughput optical I/O interface ATM switch multichip module (MCM) that has 320-ch optical I/O ports. This MCM is fabricated using ceramic (MCM-C) technology and very-small highly-parallel O/E and E/O optical converters. It uses 0.25-/spl mu/m complementary metal oxide semiconductors (CMOS) ATM switch large scale integrations (LSIs) and has a total I/O throughput of up to 160 Gb/s. A prototype module with total I/O throughput of 100 Gb/s has been partially assembled using eight optical I/O interface blocks, each composed of a 40-ch O/E converter and a 40-ch E/O converter; the data rate per channel is from dc to 700 Mb/s. Using this module we developed an optical I/O interface ATM switch system and confirmed the operation of the optical interface.

Recently, sophisticated fluidic circuits with hundreds of independent valves have been built by using multi-layer soft-lithography to mold elastomers. However, this shrinking of microfluidic circuits has not been matched by a corresponding miniaturization of the actuation and interfacing elements that control the circuits; while the fluidic circuits are small ( approximately 10-100 micron wide channels), the Medusa's head-like interface, consisting of external pneumatic solenoids and tubing or mechanical pins to control each independent valve, is larger by one to four orders of magnitude (approximately mm to cm). Consequently, the dream of using large scale integration in microfluidics for portable, high throughput applications has been stymied. By combining multi-layer soft-lithography with shape memory alloys (SMA), we demonstrate electronically activated microfluidic components such as valves, pumps, latches and multiplexers, that are assembled on printed circuit boards (PCBs). Thus, high density, electronically controlled microfluidic chips can be integrated alongside standard opto-electronic components on a PCB. Furthermore, we introduce the idea of microfluidic states, which are combinations of valve states, and analogous to instruction sets of integrated circuit (IC) microprocessors. Microfluidic states may be represented in hardware or software, and we propose a control architecture that results in logarithmic reduction of external control lines. These developments bring us closer to building microfluidic circuits that resemble electronic ICs both physically, as well as in their abstract model.

Cell Broadband Engine is a microprocessor that has very high processing performance and very high speed I/O to communicate with other devices such as system LSI and memory chips. Design optimization with statistical analysis was carried out. DOE matrix was made with dimension of signal traces and dielectric constant of the insulator in the package substrate. After major factors were detected, random sampling was done to make sure that the distribution of characteristic impedance of signal traces is within the specification. Passive characterization was carried out with test vehicle. Insertion loss and characteristic impedance is dependent on both temperature and water absorption. These environmental factors need to be taken into account when the design rule is determined. After design rule is fixed, circuit simulation for whole signal channel was carried out with considering impedance tolerance in both the package and the printed circuit board. DOE matrix was made and analyzed to determine the major factors on mid-frequency and low-frequency noise in power distribution. Inductance of package substrate and decoupling capacitor are the major effect on the mid-frequency noise, and capacitance of on-module and on-PCB affect low frequency noise. The effect of on-chip parameters was also evaluated. Several types of capacitors were characterized to measure their parasitic parameters.

The transition to the production phase of electronic products requires the product design to follow a large set of constraints that ensure that the electronic product will materialize into a viable product. The printed circuit board (PCB) design is a central part of electronic products and therefore is the part where most constraints are enforced. Although PCB designers already address design constraints with the help of Electrical Computer Aided Design (ECAD) tools that can verify product design rules in an automated manner, there are still many product design rules that are left out of the ECAD tools verification engines, in particular the design rules related to PCB manufacturing and assembly. These rules are many times verified by human visual inspection. This fact increases the risk of running into design errors, leading to increased costs during production phase. This paper proposes a rule ontology representing the large range of constraints imposed by the production phase of electronics products. The rule-based ontology is implemented using a Visual Programming Language (VPL) that facilitates the encoding of the knowledge provided by electronics products manufacturing experts. A practical example is also presented, describing a PCB manufacturing rule and its graphical representation.

Heterogenous integration is rapidly becoming important to the future roadmap of mmwave and sub-THz communications and sensing front ends. This is driven by the need for compound semiconductors which offer significant benefits in power, efficiency and footprint. This integration however is of a different nature than that for e.g. logic-memory, leading to viable solutions using interposers or printed circuit boards (PCB). We show some recent results on both interposer and PCB, with insertion losses for interconnects of the order of 1 dB and 0.1 dB respectively for D-band applications. We highlight their benefits and the challenges still present.

In order to investigate the performance potential of 3-dimensionally integrated circuits for high performance computer systems a comparative study of the interconnect structure of a RISC-processor/cache system conducted. The impact of electrical parameters of interconnection lines as well as associated package parasitics on second level cache read access is investigated for 3-dimensionally integrated circuit structures and compared to conventional PCBand advanced MCM-realizations of the system. Wiring dimensions and line drivers are optimized for the different packaging technologies and optimal realizations are compared with respect to cache access time and power dissipation. Case studies show reductions of effective switching capacitances of more than an order of magnitude and reductions of second level cache access time of over 40% for optimized 3D-systems compared to conventional PCB-realizations.

One of the grand challenges in solving the interconnection bottlenecks at the Printed Circuit Board (PCB) and Multi-Chip-Module (MCM) level, is to adequately replace the PCB and intra-MCM galvanic interconnects with high-performance, low-cost, compact and reliable micro-photonic alternatives. In our labs at the Vrije Universiteit Brussel we are therefore focusing on the continuous development of a rapid prototyping technology for micro-optical interconnect modules, which we call Deep Proton Writing (DPW).The special feature of this prototyping technology is that it is compatible with commercial low-cost mass replication techniques such as micro injection moulding and hot embossing. We will address more specifically in this paper the following components: 1) out-of-plane couplers for optical wave-guides embedded in PCB, 2) peripheral fiber ribbons and two dimensional single- and multimode fiber connectors for high-speed parallel optical connections, and 3) intra-MCM level optical interconnections via free-space optical modules. We furthermore give special attention to the optical tolerancing and the opto-mechanical integration of the components. We use both a sensitivity analysis to misalignment errors and Monte Carlo simulations. It is our aim to investigate the whole component integration chain from the optoelectronic device to the micro-opto-mechanical components constituting the interconnect module.

Technological considerations in realizing high-speed supercomputers are presented, focusing on large-scale integrated (LSI) chips, new circuit packaging technology, and a liquid cooling system. The Model SX-1 and SX-2 supercomputers employ a new circuit packaging technology achieving up to 1300 megaflops processing speeds with a 6-ns machine cycle. This new technology features a 1000-gate current mode logic (CML) LSI with 250 ps gate delay as a logic element, a I k bit bipolar memory with 3.5 ns access time for cache memory and vector registers, a 10 cm² multilayer ceramic substrate with thin film fine lines (25- \mu m width, 75- \mu m center-to-center), and a multichip package which contains up to 36 000 logic gates. A liquid cooling module is implemented for highdensity high-efficiency heat-conductive packaging for the arithmetic processor, in addition, high-density high-speed packaging of 64 kbit static metal-oxide semiconductor (MOS) RAM's are used to implement large-capacity fast main memory.