Packaging Technology for the NEC SX Supercomputer

In order to solve the thermal issue and improve the thermal resistance of LED, a device with multi-chip packaged on multi-layer composite ceramic substrate is successfully packaged. The top layer of the substrate is low temperature co-fire ceramic (LTCC), while the base layer is aluminum nitride (AINx) ceramic. 18 chips(one watt) are used in the device, and all of them are simultaneously packaged on a composite ceramic substrate which is 55 mm in length and 20 mm in width. The 18 chips are designed into two rows, and three chips in series for six parallels. At the same time the same chips are packaged on aluminum (Al) substrate and alumina (AlOx) substrate. After wire bonding photoelectric parameters of the three package modules are tested, the results show that the properties of the AINx-based package has the best performances, the thermal resistance of the device is far smaller than the other devices packed on the Al substrate and the AlOx substrate. After phosphor coatings the AINx-based multi-layer ceramic substrate package has 896.1 lm (43.4 lm/W) loading 350 milliampere (mA) to each chip, and has 1081.3 lm (35.4 lm/W) loading 500 mA. The multi-chip module has little light degradation adding 500 mA to each chip after working in the room temperature for one afternoon. At last the module is simulated by ANSYS software, the highest junction temperature of the chips in the module is about 70.8degC when 1.8 watts electric power is loaded to each chip, this temperature is far lower than 125degC which will damage the chip, and he highest simulation temperature of the aluminum heat slug is about 39.3degC. The temperature of the aluminum heat slug is about 41.0degC which is tested by thermocouple in the experiments, and it is closely to the simulation temperature 39.3degC. At last the relationship between pn-junction temperature and thermal conductivity coefficient of the silver (Ag) paste , the relationship between pn-junction temperatures and convection coefficient have been researched, the results show that the pn-junction temperature can be decreased a lot while increase the thermal conductivity coefficient of the adhesive layer or increase the convection coefficient a little.

Multichip module (MCM) technology is attracting attention from designers who need high-speed interchip connections and a reliable package for their circuit applications. This technology is being applied to realize a 1-ns cycle time 32-bit RISC processor, using 50 GHz AlGaAs/GaAs heterojunction bipolar transistor (HBT) technology and triple-level full-differential current mode logic (CML), at Rensselaer. The processor is partitioned into multiple chips due to the high power consumption and low integration level of the technology. There are several key challenges associated with this module. It has to provide high-bandwidth (/spl les/10 GHz) and high-density (/spl les/40 /spl mu/m pitch) interconnect, and dissipate nearly 250 W of power. Maximum heat flux on the MCM surface is 2.0/spl times/10/sup 5/ W/m/sup 2/. Poor heat conduction ability of GaAs chips make it tough to dissipate this hear. A methodology is developed to design a thermally stable module using a multilayer substrate with parylene as a low dielectric constant insulator, and fine pitch copper for high bandwidth lines. The design of the MCM and the thermal simulation results are presented. >

This study presents the accurate characterisation and detailed experimental study of the effect of ground-plane width and suppression of higher-order parasitic modes extending the frequency of operation up to 110 GHz for multilayer conductor-backed coplanar waveguide lines, fabricated in cost-effective thick-film multichip module (MCM) technology. The coplanar waveguides (CPWs) and components have been realised on multiple layers of dielectric onto a ceramic substrate using straightforward and cost-effective photoimageable thick-film process, demonstrating a very low loss of <0.2 dB/mm at 80 GHz for a finite ground CPW and extremely low loss of <0.1 dB at 76 GHz for CPW layer transitions, which are better than many reported results for MCM technologies. Further, the effective dielectric constant (ɛeff) and characteristic impedance (Zch) are extracted from two-port S-parameters measured on a single-line and by conversion to ABCD parameters, to investigate the practical effect of ground-plane width on CPWs on a multilayer ceramic substrate and to facilitate realisation of a cost-effective millimetre-wave MCM.

The development of Low-Density Fan-Out (LDFO), formerly Wafer Level Fan-Out (WLFO), platforms to encompass the requirements of potential new markets and applications such as the Internet of Things (IoT) is crucial to maintain LDFO as the leading Fan-Out technology. This drives the development of a new set of capabilities in the current standard LDFO process flow to break through the existing technology boundaries. One of the most widely discussed advantages of LDFO packaging is heterogeneous high-density system integration in a package. LDFO System in Package (LDFO SiP) integrates active dies, passive components and even already-packaged components using other packaging technologies. This heterogeneous integration is based on a wide range of different geometries and materials placed inside the LDFOSiP with high accuracy. Ultimately, heterogeneous integration will be fundamental to achieve new levels of miniaturization. However, multi-die solutions face several challenges such as bare-die availability, passives integration, antenna integration, low power budget, test complexity and reliability. Package research and development (R &D) must overcome all of these issues to build a product with high volume manufacturability. The wafer level SiP (WLSiP) technology required to enable the new features and processes needs to be ready for high volume manufacturing of new products at high yield and reasonable cost. This paper presents the approaches used to effectively enable LDFO SiPs (WLSiPs): 1. A pre-formed vias solution is employed to connect front to back side of the package, including development for high accuracy via bar placement. 2. A wafer front-side to back-side redistribution layer (RDL) alignment solution was developed. 3. Space requirement reduction between components to achieve the smallest possible package. 4. Miniaturized Bluetooth antenna integration in the RDL. 5. Creation of a stacking concept (vertical connections to create a modular system that enables easy addition of new features to the final product).Inside the package (excluding the area reserved for the antenna), components are densely packed: several sensors, power management components, radio communication and all required passives are incorporated into a single WLSiP. Connecting all these features to create a component that works by connecting only a single battery required implementing a double sided, multi-layer RDL, while maintaining the ability to create a 3D solution by stacking vertical connections for several other solutions. The result is an approach that easily adapts the system to a variety of customers' needs. The work done is part of the collaborative COMPETE2020-PT2020 funding program under “IoTiP-Internet of Thing in Package” project n°017763, Projetos de I &DT Empresas em CoPromoção. LDFO, LDFO SiP, Fan-Out WLP, WLSiP, SiP, Multi-Chip-Package, Antenna-in-Package, Package-on-Package, Through Mold Via, TMV®, TPV.

In this letter, a novel voltage control oscillator (VCO) is proposed and fabricated by low-temperature co-fired ceramic (LTCC) technology. Advanced three-dimensional packaging structure is utilized for size reduction by embedding passive components in multilayer substrate. According to the single π circuit configuration, the models of embedded helical inductors and coupling capacitors are established to optimize the match circuit of the VCO module. With the passive components embedded into multilayer ceramic substrate, the LTCC VCO exhibits advantages of small size and high reliability compared to conventional VCO module on PCB substrate. This proposed structural model is validated through actual LTCC process. Measured parameters show good performance and agree well with the EM simulation results. The physical dimension of the VCO module is only 10 mm×10 mm×1 mm, which makes it suitable for SIP communication system.

For an ATM switch system, we have developed a 100-Gb/s input/output (I/O) throughput optical I/O interface ATM switch multichip module (MCM) that has 320-ch optical I/O ports. This MCM is fabricated using ceramic (MCM-C) technology and very-small highly-parallel O/E and E/O optical converters. It uses 0.25-/spl mu/m complementary metal oxide semiconductors (CMOS) ATM switch large scale integrations (LSIs) and has a total I/O throughput of up to 160 Gb/s. A prototype module with total I/O throughput of 100 Gb/s has been partially assembled using eight optical I/O interface blocks, each composed of a 40-ch O/E converter and a 40-ch E/O converter; the data rate per channel is from dc to 700 Mb/s. Using this module we developed an optical I/O interface ATM switch system and confirmed the operation of the optical interface.

The LSI packaging technique utilized for the SX-3/SX-X is outlined. The VLSI chip is packaged in a chip carrier called the flipped tape-automated-bonding carrier (FTC), which has 604 input/output (I/O) bumps arranged in a matrix configuration on its bottom surface. The high-density multichip package (MCP) consists of a multilayer substrate (MLS) with a maximum of 100 FTCs and 11540 I/O pins. The MLS is a 225-mm*225-mm, 5.5-mm-thick ceramic substrate with a fine-line multilayer wiring part consisting of seven polyimide insulative layers and eight conductor layers. A multilayer board mounts the MCPs with novel zero insertion force (ZIF) connectors, and high-speed coaxial cablings are used for the interconnection system. Adoption of the ZIF-MCP connector allows insertion of multiple pin sat one stroke and high-speed interconnection. A sophisticated and reliable water cooling technique is used to cool the package efficiently. Water circulates from a cooling unit (CLU) to liquid cooling modules (LCM) that cover the MCPs. This system has a cooling capacity of up to 4-kW heat dissipation of the MCP. >

Large Scale Integration—an Appraisal

In this chapterTSV-less interposer, the recent advances in multiple systemMultiple system and heterogeneous integrationHeterogeneous integration with TSVThrough-silicon via (TSV) (through-silicon via)-less interposers (organic interposes or 2.3D IC integration2.3D IC integration) will be presented. Unlike 2.5D IC integration2.5D IC integration discussed in Chap. 3 , the TSV-interposer is replaced by the TSV-less interposers, which are meanly constructed by the fan-outFan-out packaging technology.

In the last forty years the semiconductor industry focused on the downscaling process of the CMOS (Complementary Metal-Oxide-Semiconductor) technology, trying to follow as much as possible the empirical Moore's Law. In the last five years this trend has been facing technology limits that have led to the development of a new research field, named Beyond CMOS, which investigates new electron devices concept and materials that can replace or co-integrate the standard technology, to make large scale integrated (LSI), high performance, low power devices. Carbon nanotubes (CNTs) are considered one of the most promising materials for Beyond CMOS devices, both at front-end and back-end level. The development of the research on this new organic material is due to its nanometer scale dimensions and to its outstanding electrical (metallic and semiconducting behavior, ballistic conduction, current density > 109 A/cm2) and mechanical (Young's modulus ∼1 TPa) properties, nevertheless due to its low mass (mass density ρ = 1300 kg/m3). Among the several CNT applications already reported in literature (interconnections, sensors, transistors, memory, etc.), a particular interest is on their use to build Nano-Electro-Mechanical (NEM) devices, such as resonators and switches. NEM relays based on carbon nanotubes show large-current density drive and high speed operation compared to metal-based NEMS counterparts, low actuation voltage and low power, performances which are promising for radio-frequency (RF) applications, where RF MEM devices are considered as replacement solution for their off-chip and/or solid-state counterparts in front-end transceivers. Most of the previously reported CNT NEM switches concerns relay configuration based on one single movable nanotube and its DC characterization. Despite individual proof-of-concept merits, an electromechanical switch based on a single CNT usually presents an output signal level that is too low for practical applications and a poor reliable fabrication process, which opposes the precise control at wafer level achieved by standard technology. Alternatively, a very large-scale integration of NEM devices requires the exploitation of high-density aligned arrays of nanotubes, grown in precise locations and that could be patterned into well-defined and controlled configurations. The objective of this research work was to develop LSI NEM switches based on high dense carbon nanotube arrays in the back end of the line (BEOL), with conductive and capacitive contacts and tested from DC up to high frequency (RF), in order to evaluate their performances in a wide range of operations. The synthesis process of carbon nanotubes was performed by thermal CVD and temperature, gas concentration and catalyst pretreatment were optimized to achieve high dense aligned CNT arrays. A study on the catalyst geometries and on the substrate materials were performed in order to obtain horizontal aligned arrays grown directly on metallic substrate without density change. We developed a novel surface micromachining process to suspend CNT arrays. The DC characterization of CNT NEM switches was exploited to extract the equivalent electromechanical properties of the CNT membranes, since they behave as a new body material. We extracted an equivalent flexural modulus of 8.5 GPa and a resistivity of 0.0077 Ωcm. The devices, in both configurations, present a very low actuation voltage, below 10 V, lower than typical metal NEM switch for the same dimensions and a comparable switching time. The RF characterization was performed in the telecommunication frequency range (up to 6 GHz) showing reasonably high isolation and low insertion loss. The relay shows a lower reliability than the capacitive switch, due to the elevated drive current which induces the CNTs burning at the metal-to-metal interface. The RF measurements were used to extract the parameters of the proposed devices equivalent lumped model. Several implementations of CNT NEM switches, both for DC (reconfigurable interconnects, logic functions, memories) and RF (signal routing purposes in RF system Front-Ends, phase shifting networks or digitalized capacitor banks) applications, were reported.

A novel ceramic multilayer substrate for mobile communication using alumina-glass composite ceramics and cofired copper conductors is presented. Electrical characteristics at gigahertz frequencies of the substrate, copper conductor, transmission line, and via hole were evaluated. Hybrid integrated circuits such as an antenna switch were demonstrated using the substrate. The results showed that the ceramic multilayer substrate has electrical characteristics sufficiently good for gigahertz-band applications. Using the substrates, one can greatly reduce the size of RF circuit boards for mobile communication equipment. An RF antenna switch circuit for mobile portable telephones operating at 1.5 GHz has been demonstrated. >

Recent progress in negative-working photosensitive and thermally stable polymers

Electromagnetic (EM) simulators have already become established in the design of a variety of electromagnetic devices, such as MMICs (monolithic microwave integrated circuits), antennas, shields, electromechanical machines, and magnetic circuits. Such broad applicability results from the fact that the EM simulators are software packages for numerically solving the Maxwell’s fundamental electromagnetic field equations; for the same reason, and unlike some of the other simulators, they are independent of technology, models, foundry, and other such ephemeral considerations. Although designers have long carried out electromagnetic analysis of RF components and packages where necessary, the availability of commercial EM simulators1’2 since 1989 has made this task much more common, rapid, and easier. This development parallels the concurrent development of multi-chip module (MCM) technology for high-speed digital systems, as well as the front-ends of radio-frequency (RF) systems, such as receivers, transponders, transceivers, synthesizers, and transmit-receive modules. MCMs are a modern method of electronic packaging and integration that has the advantages of low-cost, compact size, and reliability. At low speeds/frequencies, the analysis, design, simulation, layout, and verification, of MCMs requires a number of software tools for computer-aided design (CAD), including process simulators, device simulators, circuit simulators, thermal simulators, and system simulators. For high-speed and RF MCMs, the design requirements make an additional CAD tool, namely EM simulator, indispensable.

An advanced VLSI (very large scale integration) technology providing high-performance n-p-n bipolar (f/sub T/=9 GHz) and submicrometer gate-length MOS (metal-oxide-semiconductor) transistors is described. This technology is intended for high-speed logic circuits operating at 5 V, where a high level of circuit integration and low power consumption is required. Features include vertical n-p-n transistors with walled, self-aligned polysilicon emitters and lightly doped extrinsic base (LDEB) extensions MOS transistors feature complementary-doped polysilicon gates and LDD (lightly doped drain) structures for both NMOS and PMOS. Optional buried contacts between the polysilicon layer and all junctions in the silicon substrate are provided. Polysilicon emitters, MOS gates, base/collector, and source/drain regions are silicided. In addition, a fully planarized metal interconnect scheme incorporating nonselective CVD (chemical-vapor-deposited) tungsten and vertical-walled contacts and vias is utilized.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Maze routing algorithms are widely used for finding an optimal path in detailed routing for very large scale integration, printed circuit board and multichip modules. In this paper, we show that finding an optimal route of a two-pin net in a multilayer routing environment under practical via design rules can be surprisingly difficult. A straightforward extension to the maze routing algorithm that disallows via-rule incorrect routes may either cause a suboptimal route to be found, or more seriously, cause the failure to find any route even if one exists. We present a refined heuristic to this problem by embedding the distance to the most recently placed via in an extended connection graph so that the maze routing algorithm has a higher chance of finding a via-rule correct optimum path in the extended connection graph. We further present efficient data-structures to implement the maze routing algorithm without the need to preconstruct the extended connection graph. Experimental results confirmed the usefulness of our algorithm and its applicability to a wide range of CMOS technologies.