Large Scale Integration—an Appraisal

In the last forty years the semiconductor industry focused on the downscaling process of the CMOS (Complementary Metal-Oxide-Semiconductor) technology, trying to follow as much as possible the empirical Moore's Law. In the last five years this trend has been facing technology limits that have led to the development of a new research field, named Beyond CMOS, which investigates new electron devices concept and materials that can replace or co-integrate the standard technology, to make large scale integrated (LSI), high performance, low power devices. Carbon nanotubes (CNTs) are considered one of the most promising materials for Beyond CMOS devices, both at front-end and back-end level. The development of the research on this new organic material is due to its nanometer scale dimensions and to its outstanding electrical (metallic and semiconducting behavior, ballistic conduction, current density > 109 A/cm2) and mechanical (Young's modulus ∼1 TPa) properties, nevertheless due to its low mass (mass density ρ = 1300 kg/m3). Among the several CNT applications already reported in literature (interconnections, sensors, transistors, memory, etc.), a particular interest is on their use to build Nano-Electro-Mechanical (NEM) devices, such as resonators and switches. NEM relays based on carbon nanotubes show large-current density drive and high speed operation compared to metal-based NEMS counterparts, low actuation voltage and low power, performances which are promising for radio-frequency (RF) applications, where RF MEM devices are considered as replacement solution for their off-chip and/or solid-state counterparts in front-end transceivers. Most of the previously reported CNT NEM switches concerns relay configuration based on one single movable nanotube and its DC characterization. Despite individual proof-of-concept merits, an electromechanical switch based on a single CNT usually presents an output signal level that is too low for practical applications and a poor reliable fabrication process, which opposes the precise control at wafer level achieved by standard technology. Alternatively, a very large-scale integration of NEM devices requires the exploitation of high-density aligned arrays of nanotubes, grown in precise locations and that could be patterned into well-defined and controlled configurations. The objective of this research work was to develop LSI NEM switches based on high dense carbon nanotube arrays in the back end of the line (BEOL), with conductive and capacitive contacts and tested from DC up to high frequency (RF), in order to evaluate their performances in a wide range of operations. The synthesis process of carbon nanotubes was performed by thermal CVD and temperature, gas concentration and catalyst pretreatment were optimized to achieve high dense aligned CNT arrays. A study on the catalyst geometries and on the substrate materials were performed in order to obtain horizontal aligned arrays grown directly on metallic substrate without density change. We developed a novel surface micromachining process to suspend CNT arrays. The DC characterization of CNT NEM switches was exploited to extract the equivalent electromechanical properties of the CNT membranes, since they behave as a new body material. We extracted an equivalent flexural modulus of 8.5 GPa and a resistivity of 0.0077 Ωcm. The devices, in both configurations, present a very low actuation voltage, below 10 V, lower than typical metal NEM switch for the same dimensions and a comparable switching time. The RF characterization was performed in the telecommunication frequency range (up to 6 GHz) showing reasonably high isolation and low insertion loss. The relay shows a lower reliability than the capacitive switch, due to the elevated drive current which induces the CNTs burning at the metal-to-metal interface. The RF measurements were used to extract the parameters of the proposed devices equivalent lumped model. Several implementations of CNT NEM switches, both for DC (reconfigurable interconnects, logic functions, memories) and RF (signal routing purposes in RF system Front-Ends, phase shifting networks or digitalized capacitor banks) applications, were reported.

Technological considerations in realizing high-speed supercomputers are presented, focusing on large-scale integrated (LSI) chips, new circuit packaging technology, and a liquid cooling system. The Model SX-1 and SX-2 supercomputers employ a new circuit packaging technology achieving up to 1300 megaflops processing speeds with a 6-ns machine cycle. This new technology features a 1000-gate current mode logic (CML) LSI with 250 ps gate delay as a logic element, a I k bit bipolar memory with 3.5 ns access time for cache memory and vector registers, a 10 cm² multilayer ceramic substrate with thin film fine lines (25- \mu m width, 75- \mu m center-to-center), and a multichip package which contains up to 36 000 logic gates. A liquid cooling module is implemented for highdensity high-efficiency heat-conductive packaging for the arithmetic processor, in addition, high-density high-speed packaging of 64 kbit static metal-oxide semiconductor (MOS) RAM's are used to implement large-capacity fast main memory.

An advanced VLSI (very large scale integration) technology providing high-performance n-p-n bipolar (f/sub T/=9 GHz) and submicrometer gate-length MOS (metal-oxide-semiconductor) transistors is described. This technology is intended for high-speed logic circuits operating at 5 V, where a high level of circuit integration and low power consumption is required. Features include vertical n-p-n transistors with walled, self-aligned polysilicon emitters and lightly doped extrinsic base (LDEB) extensions MOS transistors feature complementary-doped polysilicon gates and LDD (lightly doped drain) structures for both NMOS and PMOS. Optional buried contacts between the polysilicon layer and all junctions in the silicon substrate are provided. Polysilicon emitters, MOS gates, base/collector, and source/drain regions are silicided. In addition, a fully planarized metal interconnect scheme incorporating nonselective CVD (chemical-vapor-deposited) tungsten and vertical-walled contacts and vias is utilized.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Chapter 3 - NEW DEVELOPMENTS IN PROGRAMMING

The entire field of application for automatic computing machines is very large. In fact, if we admit machine accounting to this field, it affects all of us in a very personal way every day. However, my remarks are to be restricted to only the application of automatic computation in aeronautical engineering, and further restricted to consider only digital computers. I shall first mention something of the reasons for automatic computation, its value and methiods; discuss briefly its future, and lastly mention some of its difficulties. First of all, what do we mean by automatic computation? As the experts would probably not agree exactly with my definition, let me beg the question and resort to example. The definition can be simplified by excluding analog computers, some of which are not truly computers at all but rather devices which simulate physical problems. By digital computer we mean a divice which solves problems digitally, or, literally, counts on its fingers. However from automatic computers we exclude desk calculators of the Friden or Marchant type. Specifically, then, this discussion is concerned with the use of IB M punched card equipment and such more sophisticated machines as the SWAC, the SEAC, BINAC, IBM's Selective Sequence Electronic Calculator, ENIAC, and certain similar machines presently being developed. These latter machines are spectacular and have been popularized in newspapers and magazines. However, practical digital computing may be said to have started about eight years ago with the widespread use of IB M punched card equipment for this purpose. Even today, by far the largest share of the actual computing is being done with standard IB M equipment. These are essentially accounting machines; indeed, their proper namre is Electric Accounting Machines. In the early days, we had a lot of trouble with such things as persuading IBM to change some machines to print minus signs instead of credit symbols to indicate -negative numbers. The proper handling of algebraic signs presented considerable difficulty, and the first multiplier which provided a reasonably direct solution for this problem was regarded with awe, much as early automobile owners viewed the self-starter. However, today's machines have come a long way and are being improved at an ever increasing rate. There must be some rather compelling reasons for the use of automatic computation. It is not cheap and provides plenty of headaches. Even a small-scale operation may cost $10,000 a month, and on a bigger scale we find that the cost of a single machine is in the order of magnitude

The development of optoelectronic components for gigabit Ethernet communications is converging towards access networks where the cost of device makes a significant impact on the market acceptance. Device fabrication and packaging cost have to be brought down with novel assembly and packaging methods. Singapore has established a reputation in semiconductor device development and fabrication with excellent process and packaging facilities. Institute of Microelectronics (IME) was founded in 1991 to add value to the Singapore electronics industry. IME is involved in the development of active and passive photonics components using Silicon and polymer materials. We present a brief report on the development activities taking place in the field of optical component packaging at IME in recent years. We present a review of our competence and some of the optical device packaging activities that are being undertaken.

The design of a digital computer for the commercial market today must, of course, face up to the pervasive influence of IBM. But technological maturity in some areas is slowing the rate of change so that designs seem to converge on certain features. Microprogramming of the native instruction set (or sets?) with emulation of a range of older systems is such a feature. Virtual memory addressing may be another. Characteristics of main storage, random access mass storage devices, data exchange media seem to converge while terminals and communications conventions proliferate and diverge. Some reasons for these phenomena are evident; others will be suggested.Whatever happened to hybrid packaging, thin films, large scale integration, and tunnel diodes? The more general question is: why do some technologies flourish only in restricted environments, or never quite fulfill the promise of their youth? Or is their development just slower than we expected? While these answers cannot be absolute, some factors affecting the acceptance of new technologies can be identified.

A system for the automatic acquisition and computation of gravity data at sea has been tested and is now operational aboard the Research Vessel CHAIN of the Wood's Hole Oceanographic Institution. This is the first recorded instance of on-line acquisition and processing of gravity data by the use of a digital computing system. Sampling and computation are performed in a one minute computation cycle making knowledge of gravity values, gravity anomalies and dead-reckoning position available in real-time. The system consists of a LaCoste-Romberg Sea Gravity Meter, data conversion units for computer compatibility with the gravity meter, ship's gyrocompass and ship's speed log, an IBM 1710 Mod 1 Control System (the combination of a 1620 Computer and a 1711 Data Converter for analog to digital conversion), and typewriter and paper tape input-output units.

The design of a high frequency (L Band), low power (2.75mW) Phase Lock Loops with a 350nm Complementary Metal Oxide Semi Conductor (CMOS) technology has been represented. The comparison of Current Starved Voltage Controlled Oscillator (CSVCO) and Differential pair VCO is performed and analyzed for low power and high frequency analysis respectively. Each component of Phase Lock Loop (PLL) is designed with 350nm CMOS technology in Design Architect Integrated Circuit Station by Mentor Graphics (Eldo-Net) as simulator. In this paper both the standard configurations have been simulated under the same environment and results are analyzed for two most important Very Large Scale Integration (VLSI)constraints, Speed (High frequency range) and Power consumption. The high speed and locking performance of the Differential pair VCO has been evaluated against the lower power consumption benefit of CSVCO.

This paper describes a novel complementary metal oxide semiconductor (CMOS) bootstrapped driver circuit for driving large resistive capacitive (RC) loads. The proposed bootstrapped driver reduces the leakage as well as process, voltage and temperature (PVT) variations from the boosted nodes with higher switching speed. Very large scale integration (VLSI) designers need boosted output for the logic circuits which are operating in ultra-deep submicron regime under widespread use of low voltage. Proposed CMOS bootstrapped driver circuit is easy in design; built with minimum number of transistors and have high boosting efficiency with sharp output performance. Comparative evaluations with existing bootstrapped driver circuits are reported. Simulation results are derived by HSPICE tool with predictive technology model (PTM) bulk CMOS process fabrication at 32 nm technology node. The ability of large leakage reduction makes this driver superior as compared to active drivers. An average of 96.97% leakage current is saved at nominal ultra-low voltage of 0.15 V. Monte-Carlo analysis indicates that the proposed bootstrapped driver has less sensitivity of PVT variations. The power consumption and delay sensitivities are reduced by 10 × and 4.12 × as compared to conventional circuit.

The increasing use of large and very large scale integration (LSI and VLSI) have introduced many difficulties in testing large logic networks. This generated the need for designing logic networks for testability. Computer algorithms for designing diagnosable metal oxide semiconductor (MOS) networks, with and without fan-in, fan-out constraints, were described in previous papers. Procedures for efficient fault simulation and test generation will be presented here. First, a basic cell model will be introduced. Next, procedures for generating a complete fault detection set for the complex cell will be given. Both minimal and near-minimal solutions will be presented for both fan-out free and arbitrary cells respectively. The efficiency of this technique will be compared with conventional testing techniques (e.g. N-dimensional path sensitization automatic test generator with a parallel fault simulator) and the results will be reported. Finally, some future work problems will be introduced and the application of this technique for improving LSI and VLSI testability will be discussed.

The Metal Oxide Semiconductor Field-Effect Transistors (MOSFET) are vital elements in designing and fabricating high-speed switching devices applicable in microelectronics, nanotechnology and Very Large Scale Integration (VLSI) designs. In this research work, an improved novel of a structure of a CSDG MOSFET was emphasized and this was applied in the modelling of a suitable mixer that replaced the conventional diode configuration. This configuration has been analyzed with its transconductance and it has been discovered that the CSDG MOSFET has better efficiency with the mixer output. Also, the thermal noise effect shows an improved output in the CSDG MOSFET, which helps in application for the nanotechnology and VLSI application.

Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability.

Technical and economic factors have caused the field of physical design automation to receive increasing attention and commercialization. The steady down-scaling of complementary metal oxide semiconductor (CMOS) device dimensions has been the main stimulus to the growth of microelectronics and computer-aided very large scale integration (VLSI) design. The more an Integrated Circuit (IC) is scaled, the higher its packing density becomes. For example, in 2006 Intel's 65-nm process technology for high performance microprocessor has a reduced gate length of 35 nanometers. In their 70-Mbit SRAM chip, there are up to 0.5 billion transistors in a 110 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip size with 3.4 GHz clock speed. New technology generations come out every two years and provide an approximate 0.7 times transistor size reduction as predicted by Moore's Law. For the ultimate scaled MOSFET beyond 2015 or so, the transistor gate length is projected to be 10 nm and below. The continually increasing size of chips, measured in either area or number of transistors, and the wasted investment involving fabricating and testing faulty circuits, make layout analysis an important part of physical design automation. Layout-versus-schematic (LVS) is one of three kinds of layout analysis tools. Subcircuit extraction is the key problem to be solved in LVS. In LVS, two factors are important. One is run time, the other is identification correctness. This has created a need for computational intelligence. Fuzzy attributed graph is not only widely used in the fields of image understanding and pattern recognition, it is also useful to the fuzzy graph matching problem. Since the subcircuit extraction problem is a special case of a general-interest problem known as subgraph isomorphism, fuzzy attributed graphs are first effectively applied to the subgraph isomorphism problem. Then we provide an efficient fuzzy attributed graph algorithm based on the solution to subgraph isomorphism for the subcircuit extraction problem. Similarity measurement makes a significant contribution to evaluate the equivalence of two circuit graphs. To evaluate its performance, we compare fuzzy attributed graph approach with the commercial software called SubGemini, and two of the fastest approaches called DECIDE and SubHDP. We are able to achieve up to 12 times faster performance than alternatives, without loss of accuracy

In this paper, a global feature extraction very large scale integration (VLSI) architecture for real-time object recognition is presented. To minimize the latency between capturing images and final recognition, the image sensor and feature extraction circuits are integrated on the same chip. The digital pixel sensor (DPS) configuration has been used because of its intrinsic compatibility with digital processing circuits. A block-readout architecture developed for DPS has been adopted for the massively parallel processing of image data. As a result, the directional edge filtering at each pixel site for local feature extraction is performed in a line-parallel manner. To eliminate trivial local features, the rank-order filter algorithm has been adapted for the processing and implemented in an efficient global feature extraction circuitry that can retain any given number of relatively more significant features in an image as essential features. This is accomplished in only 11 cycles. A proof-of-concept chip was designed in a 0.18 µm five-metal complementary metal–oxide–semiconductor (CMOS) technology, and the function of this VLSI processor was verified by circuit simulation.