Workloads for Programmable Network Interfaces

Modern high speed local area networks offer great potential for communication intensive applications, but their performance is limited by the use of traditional communication protocols, such as TCP/IP. In most cases, these protocols require that all network access be through the operating system, which adds significant overhead to both the transmission path (typically a system call and data copy) and the receive path (typically an interrupt, a system call, and a data copy). To address this performance problem, several user level communication architectures have been developed that remove the operating system from the critical communication path. The article describes six important issues to consider in designing communication protocols for user level architectures. The issues discussed focus on the performance and semantics of a communication system. These issues include data transfer, address translation, protection, and control transfer mechanisms, as well as the issues of reliability and multicast. To provide a basis for analyzing these issues, the authors present a simple network interface protocol for Myricom's Myrinet network, which has a programmable network interface. Researchers can thus explore many protocol design options, and several groups have designed communication systems for Myrinet. The authors refer to 11 such systems, all of which differ significantly in how they resolve these design issues but all of which aim for high performance and provide a lean, low level, and more or less generic communication facility.

Clustering an architecture enables hardware to operate at high clock frequencies by grouping resources into small clusters. This allows local communication within a cluster to travel shorter distances at the cost of an increased number of communications and longer inter-cluster communication latencies. Simultaneous multi-threaded architectures (SMT) allow better utilization of resources, thus a clustered SMT architecture exploits the advantages of SMT architectures and hides much of the inter-cluster communication latencies incurred due to clustering. This is achieved by executing instructions from a different thread when a thread stalls waiting for inter-cluster communication. In this work we study a new load balancing technique for an SMT clustered architecture namely, thread specific load balancing (TSLB). Unlike previous load balancing techniques that balance the load across clusters based on the total number of instructions of all threads in each cluster, TSLB allows each thread to balance its load between clusters independently. With this policy queues can take advantage of the inherent parallelism between instructions from the different threads. In previous load balancing techniques the overall number of instructions from the same thread assigned to distant clusters can be considerable, and if so, will result in high number of inter-cluster communications. In contrast, TSLB maintains an almost constant average number of inter-cluster communications due to the even distribution of instructions between clusters. We have assigned a number to each thread in each cluster that indicates the maximum number of instructions that can be executed to the specified cluster from that thread; these numbers are initially all equal but will vary with time depending on the workload of each thread. This decreases the potential queue conflicts in larger threads thus allowing them to execute faster.

This paper presents the first analysis of operating system execution on a simultaneous multithreaded (SMT) processor. While SMT has been studied extensively over the past 6 years, previous research has focused entirely on user-mode execution. However, many of the applications most amenable to multithreading technologies spend a significant fraction of their time in kernel code. A full understanding of the behavior of such workloads therefore requires execution and measurement of the operating system, as well as the application itself.To carry out this study, we (1) modified the Digital Unix 4.0d operating system to run on an SMT CPU, and (2) integrated our SMT Alpha instruction set simulator into the SimOS simulator to provide an execution environment. For an OS-intensive workload, we ran the multithreaded Apache Web server on an 8-context SMT. We compared Apache's user- and kernel-mode behavior to a standard multiprogrammed SPECInt workload, and compared the SMT processor to an out-of-order superscalar running both workloads. Overall, our results demonstrate the microarchitectural impact of an OS-intensive workload on an SMT processor and provide insight into the OS demands of the Apache Web server. The synergy between the SMT processor and Web and OS software produced a greater throughput gain over superscalar execution than seen on any previously examined workloads, including commercial databases and explicitly parallel programs.

Network interfaces for programmable NICs and multicore platforms

We systematically evaluate the performance of five implementations of a single, user-level communication interface. Each implementation makes different architectural assumptions about the reliability of the network hardware and the capabilities of the network interface. The implementations differ accordingly in their division of protocol tasks between host software, network-interface firmware, and network hardware. Using microbenchmarks, parallel-programming systems, and parallel applications, we assess the performance impact of different protocol decompositions. We show how moving protocol tasks to a relatively slow network interface yields both performance advantages and disadvantages, depending on the characteristics of the application and the underlying parallel-programming system. In particular, we show that a communication system that assumes highly reliable network hardware and that uses network-interface support to process multicast traffic performs best for all applications.

This paper presents a system architecture, data communnication scheme and application programming interface model or concept for a multiprocessor system based on a network-on-chip (NoC) platform. Each processing node connected to a mesh node has its own local (instruction and data) memory portion, and a global (shared) memory portion. The introduced communication scheme gives only a mimimum overhead in order to offer direct memory-to-memory data transfer. Each processor can make direct message delivery to another processor (producer initiated), or make a request to copy memory blocks from a remote processor (consumer initiated). The complete data transmission is handled by the network interface and a special memory controller. The network interface managed by the specialized memory controller can directly access the shared memory portion. Thus the processing node can continue its normal operation and will be not blocked during the data transfer process.

Multithreaded processors in their different organizations (simultaneous, coarse grain and fine grain) have been shown as effective architectures to reduce the issue waste. On the other hand, retiring instructions from the pipeline in an out-of-order fashion helps to unclog the ROB when a long latency instruction reaches its head. This further contributes to maintain a higher utilization of the available issue bandwidth. In this paper, we evaluate the impact of retiring instructions out of order on different multithreaded architectures and different instruction fetch policies, using the recently proposed Validation Buffer microarchitecture as baseline out-of-order commit technique. Experimental results show that, for the same performance, out-of-order commit permits to reduce multithread hardware complexity (e.g., fine grain multithreading with a lower number of supported threads).

In Simultaneous Multithreaded (SMT) architectures most hardware resources are shared between threads. This provides a good cost/performance trade-off which renders these architectures suitable for use in embedded systems. However, since threads share many resources, they also interfere with each other. As a result, execution times of applications become highly unpredictable and dependent on the context in which an application is executed. Obviously, this poses problems if an SMT is to be used in a real-time system.In this paper, we propose two novel hardware mechanisms that can be used to reduce this performance variability. In contrast to previous approaches, our proposed mechanisms do not need any information beyond the information already known by traditional job schedulers. Nor do they require extensive profiling of workloads to determine optimal schedules. Our mechanisms are based on dynamic resource partitioning. The OS level job scheduler needs to be slightly adapted in order to provide the hardware resource allocator some information on how this resource partitioning needs to be done. We show that our mechanisms provide high stability for SMT architectures to be used in real-time systems: the real time benchmarks we used meet their deadlines in more than 98% of the cases considered while the other thread in the workload still achieves high throughput.

The latency and throughput of MPI messages are critically important to a range of parallel scientific applications. In many modern networks, both of these performance characteristics are largely driven by the performance of a processor on the network interface. Because of the semantics of MPI, this embedded processor is forced to traverse a linked list of posted receives each time a messages is received. As this list grows long, the latency of message reception grows and the throughput of MPI messages decreases. This paper presents a novel hardware feature to handle list management functions on a network interface. By moving functions such as list insertion, list traversal, and list deletion to the hardware unit, latencies are decreased by up to 20% in the zero length queue case with dramatic improvements in the presence of long queues. Similarly, the throughput is increased by up to 10% in the zero length queue case and by nearly 100% in the presence queues of 30 messages

The simultaneous multithreaded [1] architecture is an extension of the single-threaded architecture that helps hide the performance penalty created by long-latency instructions, branch mispredictions, and memory accesses. Simultaneous multithreaded architectures use a more flexible parallelism, which takes advantage of both instruction-level, and thread-level parallelism. Additionally, it tends to promote better utilization of available functional units. A model of a simultaneous multithreaded architecture was designed, simulated, and analyzed in order to evaluate design alternatives. The simulator was created by modifying a version of the Simple Scalar tool set, developed at the University of Wisconsin. The simulations provide documentation for an overall system performance improvement of a simultaneous multithreaded architecture. In early simulation results, performed with the same number of functional units, an improvement in the number of instructions per cycle (IPC) of between 43% and 58% was found using four threads versus a single thread.

Algorithm, software, and hardware optimizations for Delaunay mesh generation on simultaneous multithreaded architectures

This paper presents the timing analysis methodology developed in the European project P-SOCRATES (Parallel Software Framework for Time-Critical Many-core Systems). This timing analysis methodology is defined for parallel applications that must satisfy both performance and real-time requirements and are executed on modern many-core processor architectures. We discuss the motivation and objectives of the project, the timing analysis flow that we proposed, the tool that has been developed to automatize it, and finally we report on some of the preliminary results that we have obtained when applying this methodology to the three application use-cases of the project.

In modern microprocessor and SoC designs, supply noise margin has been significantly reduced due to the continuously decreasing supply voltage level. On the other hand, with increasing current density, chips may see larger supply noise variations on various spots and from time to time. As a result, chip robustness and reliability are inevitably deteriorated with more frequent supply noise emergencies. It is therefore crucial to have an efficient supply noise prediction method to enhance design robustness. The state-of-art solutions either try to build a spatial noise estimation framework at the layout-level using the limited distributed physical noise sensors or attempt to develop emergency predictors at the architecture-level thus ignore back-end power delivery details. In this paper, we propose a cross-layer framework for temporal supply noise prediction. Our method not only accounts for the temporal characteristics of workload execution at micro-architecture-level but also incorporates the power delivery model at the circuit-level into such system-level prediction. In order to enable the capability of on-the-fly noise prediction, we first bridge the gap between system-level workload and micro-architectural-level power by employing an ordinary least square-based power estimation model and an adaptive auto-regressive integrated moving average model (ARIMA)-based power prediction model. Then a layout-level supply noise model is developed to explore the correlations between micro-architectural-level power and layout-level supply noise. Compared with existing methods, the proposed ARIMA-based power model improves the prediction performance by up to 37.5%/63.0% in X86/ARM. Moreover, compared with SPICE simulation, our framework is able to estimate present supply noise with an average error of 0.005% and predict future supply noise with an average error of 1.58%/1.17% for X86/ARM architecture.

This paper evaluates the benefit of adding a shared cache to the network interface as a means of improving the performance of networked workstations configured as a distributed shared memory multiprocessor. A cache on the network interface offers the potential benefits of retaining evicted processor cache lines, providing implicit prefetching, and increasing intra-cluster sharing. Using simulation, eight parallel scientific applications were used to evaluate the performance impact of a shared network cache. In each case, we examined in detail the means by which processor cache misses were satisfied. For the applications studied, we found that the network cache offers substantial performance benefit when processor caches are too small to hold the application's primary working set, or when network contention limits application performance. The expected benefits of implicit prefetching and increased intra-cluster sharing did not contribute significantly to the performance enhancement of the network cache for most applications. Finally, the advantage afforded by the network cache diminishes as processor cache size increases and network contention decreases.

This paper endeavors to delve into the inheritance pathways and commercialization strategies of traditional Chinese embroidery patterns against the backdrop of the digital-intelligence era, with a particular focus on Hubei Han Embroidery, a non-material cultural heritage that embodies profound cultural depths and unique artistic values. As technology advances rapidly, digital-intelligence technologies present unprecedented opportunities and challenges for the preservation and transmission of traditional cultures. By analyzing the artistic features, cultural connotations, and current state of inheritance of Han Embroidery patterns, this study integrates cutting-edge theories from the field of design studies to propose a series of strategies that foster the inheritance and development of Han Embroidery patterns in the new era.Firstly, the paper traces the historical origins of Han Embroidery, elucidating its artistic charm and craftsmanship as a significant representative of Jingchu culture, encompassing intricate stitchwork, rich color utilization, and profoundly symbolic pattern designs. Subsequently, it delves into the impacts of the digital-intelligence era on the traditional embroidery industry, highlighting the potential and application prospects of digital technologies such as 3D scanning, Virtual Reality (VR), Augmented Reality (AR), and Artificial Intelligence (AI) in preserving, replicating, innovating, and disseminating embroidery patterns.In terms of inheritance strategies, this paper underscores the significance of constructing digital platforms. By establishing a Han Embroidery pattern database and developing interactive experience applications, it aims to facilitate the widespread dissemination and popularization of Han Embroidery culture. Concurrently, it advocates a cross-disciplinary fusion approach, encouraging the integration of Han Embroidery with modern design, fashion industries, and cultural creativity sectors to create new products that align with contemporary aesthetics while embodying the essence of traditional culture. Furthermore, the paper discusses innovations in talent cultivation and educational models, advocating for the establishment of an integrated industry-academia-research inheritance system to nurture a new generation of inheritors who are proficient in both traditional craftsmanship and modern design skills.Regarding commercialization strategies, this paper analyzes shifts in market demands and consumer preferences, proposing precision positioning, brand-oriented operations, and online-offline integration strategies to enhance the market competitiveness and brand influence of Han Embroidery products. Through various channels such as hosting cultural festivals, participating in international exhibitions, and expanding e-commerce platforms, it seeks to broaden the market reach of Han Embroidery products, thereby achieving a win-win situation between economic benefits and cultural inheritance.In conclusion, from a design studies perspective, this paper provides an in-depth exploration of the inheritance and commercialization strategies of traditional Chinese embroidery patterns in the digital-intelligence era, taking Hubei Han Embroidery as a case study. It presents practical proposals and recommendations aimed at contributing wisdom and momentum to the innovative development and sustainable inheritance of traditional Chinese culture.