There has been a great deal of interest in recent years relating to the use of direct liquid immersion cooling for heat dissipation from microelectronic components. The high levels of circuit integration place size constraints on any techniques used for heat removal. This paper presents results obtained using a novel heat sink which addresses the need for a mechanism to remove high heat fluxes, while at the same time dealing with space limitations. This heat sink consists of cavity structures etched into a silicon surface, utilizing manufacturing processes similar to those used in the production of the chips themselves. The enhanced surface features are in the form of pyramidal cavities with a mouth size as low as 12 μm, and cavity density as high as 420 cavities/cm2. Tests were conducted using thin film heaters deposited on a silicon surface as the heat source. Data obtained from a bonded heat source–heat sink combination indicated very low values of overshoot at boiling incipience. The cooling characteristics of these etched silicon heat sinks were studied in two dielectric fluids; R-113 and FC-72. The boiling performance of an epoxy bonded heat sink was compared with that of a direct bonded heat sink.

A numerical model was developed to describe the liquid and vapor flows inside porous wicks in heat pipe evaporators. The parametric effects of the wick design parameters, including pore radii distribution, wick permeability and thickness, were studied for various heat flux conditions. The vapor fraction, defined as the percentage of wick volume occupied by the vapor, was found to be highly dependent on the pore radii distribution and critical in determining the heat flux limit of the evaporator. The model was compared to previous experiments and other models to verify its accuracy. It can be used for the design of high heat flux heat pipes for cooling of high power electronics.

This paper presents a computer model with the use of a finite-volume scheme on the liquid flow and heat transfer in microchannels, with streaming potential as the driving force. The concept of electric double layer (EDL) was introduced to explain the microscale deviation. Interfacial electrokinetic phenomena such as the EDL play important roles in various transport processes in microchannels. Conventional theories of fluid mechanics and heat transfer cannot explain these phenomena observed in microchannels. The presence of the EDL reduces the liquid velocity within the microchannel, which affects the heat transfer mechanism in the pressure-driven microchannels. In this paper, a source term in the form of the electrical body force was included in the governing momentum equations for microscale computation with the effects of the heat transfer through the channel wall. The numerical parametric studies performed allowed the conclusion that the flow and heat transfer characteristics in microchannels depend on the bulk ionic concentration, the Zeta potential and the aspect ratio of the channel, which is the reflection of the EDL effects. The existing of the EDL is more significant as aspect ratios decrease. Also, the friction coefficient increases as the ionic concentration of the aqueous KCL solution decreases and the Zeta potential of the system increases. However, one should be aware that the ionic concentration of 10-8 M is unlikely in reality.

Factorial experiments were carried out to study the effects of the average cathodaic current density, electrode separation, and the active area density on the workpiece-level plating thickness variability for an acid copper pattern electroplating process. All the three parameters and the current density × electrode separation interaction were found to be significant, and an eight-term first-order prediction model was constructed and verified experimentally. The minimum variability achievable was found to increase with the active area density contrast over the board surface, and was explained by the scattering effect of the density contrast on the average plating thickness. Furthermore, these experiments showed that the pattern-level variation was different even though the two patterns have identical local average active area density and density contrast if their individual feature sizes are different. This suggested an interaction effect between the overall active area density and the density contrast of the substrate, and the possibility of further reducing the workpiece level variability by careful manipulation of such interaction.

Screen printing has been the dominant method of thick film deposition because of its low cost. Many experiments in industry have been done and many models of the printing process have been developed since the 1960's. With a growing need for denser packaging and a drive for higher pin count, screen printing has been refined to yield high resolution prints. However, fine line printing is still considered by industry to be difficult. In order to yield high resolution prints with high first pass yields and manufacturing throughput, the printing process must be controlled stringently. This paper focuses on investigating the effect of manufacturing process parameters on fine line printing through the use of statistical design of experiments (DOE). The process parameters include print speed, squeegee hardness, squeegee pressure, and snap-off distance. Response variables are space widths of 10 mil, 8 mil, and 5 mil lines in both parallel and perpendicular directions relative to the squeegee travel direction. It is concluded that the squeegee hardness and print speed have statistically significant effects on print quality. The harder the squeegee hardness and the lower the print speed within the range of values tested, the better the printed results. It was observed that the space width between perpendicular lines is narrower than that of parallel lines. The implementation procedures of the experimental design are also presented. The analysis of a 2k factorial design with center points pertaining to the fine line printing experiment is discussed in detail.

A study is carried out to investigate the characteristics of turbulent fluid flow and heat transfer in the entrance region of a flow channel containing heat-generating modules of different sizes and distributions. The flow is described by Reynolds averaged Navier–Stokes equations and k-e model with wall function treatment. The prediction for flow and heat transfer characteristics has been made and compared with published experimental results. The computational results showed good agreement for performance parameters such as Nusselt numbers and Coefficient of pressure with experiments. The investigation is performed for Reynolds number values of 5000 and 15,000, and for two different geometrical configurations. Flow and heat transfer characteristics with varying parameters are also discussed.

Ink-jet/micro-jet printing methods are being developed for direct writing of a variety of materials for electronics and optoelectronics manufacturing. The advantages offered by this approach for micro-element fabrication and adhesive joining include precise volumetric control of dispensed material, data-driven flexibility, low cost, high speed, and low environmental impact. Custom thermo-setting and thermoplastic systems have been developed for the printing of optical interconnects, dielectric elements and coatings, adhesives and thick film resistors, utilizing a drop-on-demand piezoelectric print head operable at temperatures up to 300°C. Reviewed here are examples of printing of (a) adhesives for component bonding; (b) dielectrics for overcoating and conformal microelectronics fabrication; (c) thick-film resistors; (d) micro-optical components; (e) polymers filled with oxides and fluorescing materials and (f) solder bumps. Manufacturing applications potentially addressable to advantage by this method include flip chip die attach, chip-scale microelectronics packaging, underfilling and overcoating, along with fabrication of passive devices, disk drive heads, and flat panel displays.

Advanced electronics assembly based on direct attachment of semiconductor devices to printed circuit boards is a rapidly growing technology. Direct chip attach (DCA) or flip chip on board (FCOB) processing typically requires the application of underfill materials in order to achieve adequate reliability for commercial electronic applications. Unfortunately, flip chip on board processing has yet to become a low-cost, high-throughput process compatible with high-volume electronics packaging and high-volume surface mount processing. In order for FCOB processing to be high volume, electronics packaging and SMT-compatible, innovative techniques for underfill processing are required. This paper analyzes underfill processing in order to assess manufacturablity in terms of productivity and cost. In particular, four techniques for underfill processing are analyzed, including capillary flow, vacuum-assisted capillary flow injection flow, and compression flow processing.

As the portable electronics industry continually drives electronic assemblies to higher functionality in smaller form factors, material compatibility and thermal dissipation issues are becoming considerably more acute. Most of the current approaches attempt to marry conventional materials technologies in order to achieve as much leverage as possible out of the established infrastructure. However, concurrent engineering of reliable, high-density electronic assemblies will require the introduction of a new material technology.A novel base technology that is applicable to all of the major packaging and redistribution elements in an electronic module is presented. A single family of polymer/metal composite conductors can be used for chip packaging redistribution layers, multichip module or multilayer PWB interconnects, and SMT assembly. High-density multilayer circuits with landless blind and buried vias can be fabricated by filling the conductor paste into photoimaged dielectrics and thermal processing. Via layers are prepared directly on the inherently planarized circuit layer in an identical fashion. Building up layers sequentially in this manner results in multilayer circuits built on a single substrate layer and minimizes the number of interfaces between dissimilar materials. Because these composite materials are applied in an additive fabrication method, metal substrates can be employed for high thermal dissipation and excellent CTE control over a wide temperature range. Two variants of the composite conductor can successfully replace solder for surface mount and chip on board assembly. These reliable, highly-thermally and electrically conductive materials are compatible with the standard metal finishes of conventional technologies and can be adopted piecemeal as desired; however, the largest reliability and cost benefit is realized when all of the elements are used in conjunction with one another.The conductor materials are based on interpenetrating polymer and metal networks that are formed in situ from metal particles and a thermosetting flux/binder. The metal network is formed when the alloy particles melt and react with adjacent high-melting point metal particles. Interaction also occurs between the alloy particles and pad, lead or previous trace metallizations provided they are solderable by alloys of tin. The new alloy composition created by the interdiffusion process within the bulk material has a higher melting point than the original alloy and thus solidifies immediately upon formation. This metallurgical reaction, known as transient liquid phase sintering, is facilitated by the polymer mixture. Integration of the polymer and metal networks is maintained by utilizing a thermosetting polymer system that cures simultaneously with the metallurgical reaction. Although similar in concept and performance to cermet inks, these compositions differ in that their process temperatures are compatible with conventional printed wiring board materials and that the polymeric binder remains to provide adhesion and fatigue resistance to the metallurgical network.

Journal of Electronics ManufacturingVol. 06, No. 04, pp. 317 (1996) Book ReviewNo AccessBook Review: "High-Frequency Analog Integrated Circuit Design", Ravender Goyal (Editor)Terry EdwardsTerry EdwardsDepartment of Manufacturing Engineering, Loughborough University, Loughborough, Leics, LE 11 3TU, UKhttps://doi.org/10.1142/S0960313196000263Cited by:0 PreviousNext AboutSectionsPDF/EPUB ToolsAdd to favoritesDownload CitationsTrack CitationsRecommend to Library ShareShare onFacebookTwitterLinked InRedditEmail John Wiley & Sons, Inc. 1995 FiguresReferencesRelatedDetails Recommended Vol. 06, No. 04 Metrics History PDF download