Book Chapter310.1201/b22393-18Quality Control in ManufacturingMay 11, 2018ManufacturingZainul HudaCiteListenSave
Book Chapter10.1201/b22393-19Economics of ManufacturingMay 11, 2018ManufacturingZainul HudaCiteListenSave
Book Chapter10.1201/b22393-6Metal Forming II—Bulk DeformationMay 11, 2018ManufacturingZainul HudaCiteListenSave
Book Chapter10.1201/b22393-5Metal Forming I—Deformation and AnnealingMay 11, 2018ManufacturingZainul HudaCiteListenSave
Book Chapter10.1201/b22393-10Machining III—Shaping, Milling, and GrindingMay 11, 2018ManufacturingZainul HudaCiteListenSave
Conference Article110.1615/ihtc13.p13.20THERMAL ANALYSIS USING INVERSE TECHNIQUE APPLIED TO AN ALUMINUM ALLOY GTAWJan 01, 2006ManufacturingS R Carvalho + 2 more +2CiteListenSave
Conference Article110.1615/ihtc13.p13.10INTERACTION BETWEEN THE FLOW CONDITIONS AND TEMPERATURE DISTRIBUTION IN THE CONTINUOUS SLAB CASTER MOLDJan 01, 2006ManufacturingP R Scheller + 2 more +2CiteListenSave
Conference Article1110.1115/imece2003-42149Prime Silicon and Silicon-on-Insulator (SOI) Wafer Polishing With Magnetorheological Finishing (MRF)Jan 01, 2003ManufacturingMarc Tricard + 3 more +3The December 2001 [1, 2] edition of the International Technology Roadmap for Semiconductors [3] (ITRS-2001) identifies several challenges for the manufacturing of silicon and silicon-on-insulator (SOI) wafers. For silicon, edge exclusion, site flatness and nanotopography1 requirements will become extremely challenging. For SOI, requirements for the control of the top silicon layer and its associated uniformity are pushing the limits of metrology. Keeping ± 5% tolerances on thicknesses, gradually decreasing from more than 100nm to less than 20nm for partially depleted devices (let alone from 30 to 3nm for fully depleted devices) is exceeding the capabilities of traditional chemo-mechanical-polishing (CMP) processes [5]. This paper will briefly describe magnetorheological finishing (MRF) and its suitability for prime silicon and SOI wafer polishing. Particular emphasis will be placed on MRF’s ability to improve the global flatness and the total thickness variation (TTV) on prime silicon wafers, and to reduce the nominal thickness of the top silicon layer, while improving thickness uniformity on SOI wafers. The paper will also touch upon the process qualification issues associated with the tight requirements of the semiconductor industry.Read moreCiteListenSave
Conference Article2410.1115/imece2003-41809Comparison of Analytical and Numerical Simulations for Variable Spindle Speed TurningJan 01, 2003ManufacturingTama´s Insperger + 3 more +3The turning process with varying spindle speed is investigated. The well-known single degree of freedom turning model is presented and the governing delay-differential equation with time varying delay is analyzed. Three different numerical techniques are used to solve the governing equation: (1) direct Euler simulation with linear interpolation of the delayed term, (2) Taylor expansion of the time delay variation combined with Euler integration and (3) semi-discretization method. The results of the three method are compared. Stability charts are constructed, and some improvements in the process stability is shown, especially for low spindle speed domains.Read moreCiteListenSave
Conference Article410.1115/imece2003-41694Requirements for Consistent and Productive Performance in High Speed MillingJan 01, 2003ManufacturingKeith A Young + 1 more +1The major performance constraint in high speed milling operations is tool chatter. This is especially true when using long slender tools. Much recent research has been done to improve the performance of milling operations through choosing tool lengths and spindle speeds such that tool chatter is avoided. This paper describes two criteria for choosing productive lengths of tools.Read moreCiteListenSave