ABSTRACT PPt developed the FO-PLP (fan out-panel level packaging) technology platform is called C3iM (copper connection component in material), which uses chip-first and face-up methods to embed components. In order to meet the needs of products with high current, high voltage, heat dissipation requirement and high reliability, such as power electronic components for server and automotive, C3iM adopts thick Cu and high Cu pillar for layer to layer connection technology. Compared to FO-WLP (fan out wafer level package), C3iM is higher in performance and can be used in power components, automotive power IC and other fields. For example, semiconductor power components such as SiC or GaN applied to high-voltage and high-frequency product applications, must face the challenges of heat dissipation, electrical performance, and reliability. The unique packaging technology of C3iM can overcome these difficulties and produce the products that meet customer needs. The development of PPt C3iM has been completed and has already high volume production for automotive product.

ABSTRACT As advanced packaging continues to drive towards heterogeneous integration, new materials need to be developed to address the many challenges faced in the assembly process. This presentation will focus on innovative materials for advanced packaging, particularly for small form factor modules, including novel flux formulations for flip chip attach that are compatible with underfill and molding compound, an adhesive agent for fluxless soldering with a formic acid atmosphere, solders with various temperatures for hierarchical soldering. The technology drives toward increased functionality, better efficiency, and higher power density; advanced packaging silicon chip/die size is now bigger, with densely packed interconnect, tighter pitch, and smaller bumps. Some of the common issues we observed due to these are warpage-induced open joints from the big and thin die, flux residue removal challenges due to the tight spacings, and thermal-induced reliability issues. Novel flux formulations and adhesive agents for wafer/die bonding are needed, and interactions between the flux material and various dielectric materials on the wafer need to be better studied. The shift towards using semiconductor-grade ultra-low residue no-clean flip-chip fluxes, which eliminates the cleaning process, is one of the solutions for overcoming these challenges. Another possible solution, studied in recent years, is using a near-zero residue fluxless adhesive agent to hold the die in place while reflowing in a formic acid reflow atmosphere. The development of new solders is also a critical enabler for heterogeneous integration. If there are different reflow cycles that require a solder hierarchy, alloys with varying melting temperatures may be needed for SIP. In addition, lower melting-temperature solders can provide better warpage control, especially for thin die and substrate, as well as for heat-sensitive sensors, die, or substrate that require low-temperature processing. Alloys with enhanced reliability are also needed for certain SIP modules. In summary, proper selection and application of interconnect materials for various assembly processes is crucial to ensuring high production yield for the assembly process of advanced packaging and SIP application.

ABSTRACT The semiconductor industry is continuously evolving to meet the demands of an increasingly connected and data-driven world. As traditional Moore's Law scaling becomes more challenging, the next frontier in advanced packaging is heterogeneous integration (HI), with an emphasis on key technologies such as silicon interposers, hybrid bonding, and fan-out wafer-level packaging (FOWLP). HI involves combining various components and technologies, including diverse materials, devices, and functions, within a single package to enhance system performance, functionality, and miniaturization. This paper explores the emerging paradigm of heterogeneous integration with a focus on these key enabling technologies. I will discuss the principles and capabilities of silicon interposers, which provide a versatile platform for integrating different semiconductor components, reducing interconnect length, and enhancing signal speed and power efficiency. Hybrid bonding, a revolutionary technique for precise, low-temperature chip-to-chip connections, is another critical aspect, enabling a new level of flexibility in the assembly of complex systems. Furthermore, I will examine the advantages and versatility of Fan-Out Wafer-Level Packaging (FOWLP), which enables the integration of multiple semiconductor devices and heterogeneous components on a single wafer. This approach not only reduces form factors but also offers cost-effective and high-performance solutions for a wide range of applications. This paper discusses how the synergy of silicon interposers, hybrid bonding, and FOWLP has brought about the benefits of HI, such as improved system performance, cost-effectiveness, and time-to-market acceleration. These technologies enable the industry to address the challenges posed by the limitations of traditional scaling, enhancing system capabilities and performance in various applications, including high-performance computing, artificial intelligence, 5G communications, automotive electronics, and healthcare devices. An overview of these three core HI platforms will be presented along with applications areas.

ABSTRACT The growth of artificial intelligence, especially recent development of ChatGPT, demands for much higher data rate. Chiplet package has been the most possible alternative solution with Moore's law comes to end. Fan-Out Multi Chip Module (FOMCM) is one of chiplets that designed for lower cost and high data rate transmission package. Wafer Level FOMCM manufacturing is currently done on wafer level up to 12″/300 mm. For higher productivity and therewith lower costs, larger form factors are introduced. Instead of following the wafer level roadmaps to 450 mm, panel level packaging might be the next big step. Considered panel dimensions ranges from 300×300 mm 2 to 510×515 mm 2 up to 600×600 mm 2 . In this study, we have developed a very large chiplet package using panel level FOMCM technology. This package has the Fan-out size of 30 * 47 mm 2 and contained 2 integrated dies. These 2 chips are attached on the three prefabricated redistribution layers (RDLs) with Flip-chip (FC) process. This process performs on a glass panel with size 510 * 515 mm 2 . In addition, main challenges as panel warpage, fine line space RDL in panel level packaging will be discussed.

ABSTRACT As packaging drives to extend the capabilities of Moore's Law via heterogenous integration, numerous bonding technologies have emerged as potential pathways, allowing for integration of both a variety of devices in the lateral space as well as vertical integration of chips via stacking. As vertical integration on interposer becomes more complex due to shrinking CDs and increasing die layers, alignment and shape control in the bonding process becomes critical. Thermocompression bonding (TCB) is particularly well-suited for larger die, where localized reflow allows a better control of chip gap height and tilt throughout the bonding process. TCB systems require both high accuracy and repeatability in all dimensions to provide a reliable system in package. While a 2D system can provide a plan view assessment of a single bond layer between two chips, it falls short in characterizing the critical z-dimension in a highly integrated chip stacking scenario. Therefore a robust solution is needed for both system alignment validation in the x,y plane as well as a capability to explore gap height and bump quality/buried issues in high aspect ratio TSV. This paper will explore an x-ray application of a stacked 15-layer die-to-interposer structure to qualitatively validate overall health of the TSV (bond, pad, fill) via a nondestructive volumetric method as well as quantitatively evaluate stacked die for via/ball/pad alignment to determine overall alignment shift during the bonding process. In the test vehicle for a flip chip FO-WLP process flow first presented by IMEC, a silicon (Si) bridge is utilized to connect the logic and through-package via dies with a bump pitch of 20μm for the logic die interconnect. This is done by carefully aligning the logic dies on the carrier and then placing the through-package dies aligned to the carrier and logic dies. In die final step, a high accuracy placement and stacking TCB tool attaches the Si bridge. To perform an accurate assessment for bump alignment and bond quality, an initial high-resolution 3D x-ray scan is performed on a 1.5mm 3 region of interest with over 2,000 individual projections at a 1.4μm voxel resolution with a 4x objective, taking approximately two hours. The dataset is put through a deep-learning algorithm which generates an AI model. This model is then applied to a faster scan of 15 minutes with a 1,4μm voxel resolution for the same field of view (FOV) on a nearby array and the data is collected and processed. To verify alignment of the entire sample, data is collected on the tightest pitch (in this case 20μm) oriented in both the vertical (x) and horizontal (y) plane in the through-silicon via (TSV) region. The z-plane is analyzed and processed by computer vision algorithms, and individual interconnects are then quantified and sorted for solder height (z), width (x,y) and TSV misalignment (deviation from expected center, x 1 y 1 -> x 2 y 2 ). To validate the model, a high-resolution 20h scan with standard reconstruction and a 15min scan based on deep learning are collected for the same region of interest (ROI). The data is comparable. Furthermore, the global misalignment data between both datasets demonstrates similar misalignment propagating through the 15-layer stack.

ABSTRACT The digital content of our lives and societies has been recently exploding to a rate that only few could have imagined no more than five or ten years ago. High-end smartphones, cloud and edge computing, autonomous driving, artificial intelligence, high-performance computing for desktops and laptops, energy-savvy wearables and portables have forged new and unprecedented challenges in terms of complexity and performance of semiconductor chips. In the first section, this paper discusses the limitations of the current “Moore era”-driven approach to the design and manufacturing of microprocessors and large system-on-chip, the evolution to the “post-Moore era”, dominated by the so-called chiplets, and various platforms for heterogeneous integration . In the second section, a novel technology based on chip-last fan-out process developed by JCET Group, is presented.

ABSTRACT Advanced packaging has continued to evolve in order to meet the different needs of the industry-from the deployment of 5G, the broad usage of artificial intelligence, the surge of internet traffic, to the growth of electronics content in automotive, among others. Multi-die, embedded die, 2.5D, 3D, TSMC's SoIC & CoWoS, Samsung's CUBE and Intel's Foveros, are some of the examples of highly integrated advanced packaging solutions. Different types of interconnect technologies, e.g. chip on chip, chip on wafer/substrate and wafer on wafer, with different assembly processes, are used to optimize the yield of such packages, while new and innovative materials need to be developed to address the many challenges faced in the assembly process. This work will introduce different assembly processes and the associated materials, and the benefits and disadvantages of the various options will be discussed in detail. Proper selection and application of interconnect materials for the various assembly processes is crucial to ensuring high production yield for the assembly process for reliable wafer-level packages.

ABSTRACT Acoustic Microscopy (AM) techniques have been utilized by labs within the microelectronics industry for failure analysis and quality assurance testing of front-end and back-end for many years. As Wafer Level Packages (WLPs) become more common and the manufacturing processes have become more standardized there has been a push toward more integrated process control system for WLPs as well. Initially standard AM lab systems were utilized with skilled operators trained to inspect and interpret the results. As volume increased improvements to the throughput were made by simplifying the operator handling of devices/parts to be screened in trays or wafer fixtures for modified laboratory systems. Eventually the increases in the volume led to operator fatigue, leading to poor interpretation of the data and miss-handling. A fully automated AM system was initially done for front-end processes, such as SOI bonded wafers, with integrated handling, AM scanning, drying and image analysis. Then there was a push for AM process control in the back-end manufacturing processes with parts handled within JEDEC trays. Since then, monitors have been added to determine and compensate for small process variations and to match systems from site to site for consistent, reliable data for total process/quality control. This presentation will discuss the development of the AM techniques and system controls that can be integrated into a WLP manufacturing process for reconstituted wafers or panels to ensure you are within control limits and providing higher yields.

ABSTRACT The digital transformation has required the exascale computing with high frequent access to data to fulfil high performance applications. The massive amount of data is raising a problem of operational and storing cost of the data. Meanwhile, the exponential cost of silicon scaling has created an inflection point for the industry. Die partitioning and chiplets integration offer a compelling value proposition to improve yield and accelerate performance and power efficiency. It is driving the development of advanced packaging technology to enable chiplets integration with separate designs and different manufacturing process nodes for IP reuse, performance and cost optimization, as well time to market reduction In this paper, different advanced Fanout Chip on Substrate (FOCoS) technologies have been developed for chiplets heterogeneous integration applications. FOCoS chip first (FOCoS-CF), FOCoS chip last (FOCoS-CL) and FOCoS embedded Si bridge (FOCoS-B) will be discussed. The schematic structures and process flows for each FOCoS technology will be introduced accordingly. Furthermore, the test vehicles (TV) for chiplets integration by using various FOCoS technologies have been presented in this paper. The high density FOCoS with RDL line and space 2/2um was demonstrated. The key process factors to achieve fine RDL quality were also discussed in this paper. Finally, the comparison on warpage for chiplets integration among various FOCoS technologies have been elaborated.

ABSTRACT Over the coming decade, advanced packaging will become increasingly critical to performance, cost, and density improvements in advanced electronics. There is both an industry push: cost and performance advances in transistor scaling are increasingly difficult. And there is an industry pull: customization for each market can be done far more quickly by assembling a series of parts in a package, rather than by design and integration into a single device. This isnt a new idea: Gordon Moore said “ It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected. ” In the early years, this integration happened at the system level: GPU cards, sound cards, match coprocessors, and communication devices. In the 2000’s, this switched to integration of major components on die. And now, the same concept returns in integration on the local interconnect level. Manufacturing will necessarily advance in the packaging arena: pin density and package size will both increase to support the high bandwidth and device integration demands. Local bandwidth has expanded by 10x, which gives rise to 10x higher pincounts. Similarly, lower latency requirements require small, low delay interconnects. The downside of multiple device integration is a higher set of requirements on the reliability of both the individual devices and the fully assembled system. This is an opportunity to take advantage of new strategies and technologies in package inspection. The sampling challenges for both control and inspection for high reliability require systems that can run at 100% coverage and millions of units per year at (tens of) thousands of bumps per device. An overview of reliability sampling challenges as it relates to the end of line inspection, as well as sampling for both defect type and incidence is critical to understanding how and what to measure to maximize yield. There are fundamental tradeoffs between speed, resolution, and signal to noise ratio that inform a systematic engineering understanding of inspection. Optimizing that trade-off specifically for semiconductor inspection leads to dedicated tools with extremely high resolution, speed, and low dose. This does require rethinking some basic assumptions in the design of semiconductor inspection systems. To take advantage of this speed, fully automated systems are needed to identify and classify defects found at th bump level. In parallel with the speed requirements, sensitivity, and noise immunity can be improved with an understanding of the systematic sources of noise. These can be mitigated and even eliminated with novel algorithms for both image enhancement and defect location.