Memory Address Research Articles (Page 1)

M3SPCL: Multi-stage multi-grained multi-view supervised prototypical contrastive learning.

Dose calculations in proton therapy require the fast and accurate solution of a high-dimensional transport equation for a large number of (pencil) beams with different energies and directions. Deterministically solving this transport problem at a sufficient resolution can however be prohibitively expensive, especially due to highly forward peaked scattering of the protons. We propose using a model order reduction approach, the dynamical low-rank approximation (DLRA), which evolves the solution on the manifold of low-rank matrices in (pseudo-)time. For this, we compare a collided-uncollided split of the linear Boltzmann equation and its Fokker-Planck approximation. We treat the uncollided part using a ray-tracer and combine high-order phase space discretizations and a mixture model for materials with DLRA for the collided equation. Our method reproduces the results of a full-rank reference code at significantly lower rank, and thus computational cost and memory, and further makes computations feasible at much higher resolutions. At higher resolutions, we also achieve good accuracy with respect to TOPAS MC in homogeneous as well as heterogeneous materials. Finally, we demonstrate that several beam sources with different angles can be computed with little cost increase compared to individual beams.

Memristor-based analogue computing in memory (CIM) offers revolutionary gains in energy efficiency and computing power for data-intensive applications such as artificial intelligence. However, it typically struggles with achieving high accuracy at the same time, owing to the noise-sensitive nature of analogue computing and the non-ideal characteristics at the device and circuit levels that inevitably result in computing errors. Although progress has been made in device engineering and hardware-algorithm co-optimization to mitigate the error and parasitic effects, many of these advances inadvertently incur a hardware or energy consumption overhead, undermining the core benefits of analogue CIM. This Review dissects the computing error sources across the CIM hierarchy from the memristor device and array to the system architecture and algorithm, and evaluates the strategies to minimize those errors. We highlight the material and device innovations, array-level techniques and algorithm-architecture co-design frameworks towards high-accuracy analogue CIM. By dissecting the trade-off between computing accuracy and implementation cost, this Review draws a roadmap for translating memristor-based analogue CIM technology from proof-of-concept prototypes to large-scale deployment for accelerating next-generation artificial intelligence.

ABSTRACT The present study examined the association between acculturation orientations and the phenomenological and episodic characteristics of autobiographical memories of Syrian adult migrants in Türkiye. Moreover, the role of language in this association was investigated. Each participant received three instructions: recalling a pre-migration memory, a post-migration memory, and projecting an autobiographical future event. Participants then rated the general phenomenological and episodic characteristics of each memory, as well as the episodic characteristics of autobiographical future projection. Results revealed that host cultural orientation was positively associated with all characteristics of post-migration memories, as well as with the episodic characteristic of autobiographical future projection. The interaction pattern of acculturation orientations showed that the separation strategy was positively associated with post-migration autobiographical memory variables. No statistically significant associations were found between language and autobiographical memory variables. To the best of our knowledge, this study is the first to examine migrants’ autobiographical memory characteristics across different life periods by measuring acculturation. Overall, the findings suggest that the adaptiveness of different acculturation strategies for autobiographical memory recall may be highly dependent on the sociocultural context of the host country. The findings indicate new conceptualizations in migrants’ autobiographical memory research and address gaps in the existing literature.

While oxide-based memristors enable CMOS-compatible in-memory computing, their confinement to single-material memristive layers restricts heterogeneous interfacial engineering-limiting neuromorphic adaptability. Here, a unique nanobrush-based Y2O3/CeO2 superlattice structure with an average height of 75nm is fabricated using diffusion-limited laser epitaxy. Atomic-resolution structural characterization reveals that each Y2O3/CeO2 superlattice nanobrush exhibits self-organized heterogeneous interfaces along (111) crystallographic orientation. Notably, the nanobrush memristor exhibits unipolar switching with a RON/ROFF ratio ∼12 higher than film-based superlattice devices, plus excellent endurance (1000 cycles) and retention (104 s). The enhanced resistive switching in nanobrush memristors likely stems from their brush geometry and space charge enrichment at chevron-like heterointerfaces. XPS analysis confirms abundant oxygen vacancies in the nanobrush-based superlattices, generating substantial mobile ionic defects. The vertically-aligned nanobrush geometry provides abundant conduction pathways for oxygen vacancy migration. Ultimately, these fluorite-bixbyite superlattice nanobrushes demonstrate structurally engineered, energy-efficient, noise-resistant memory for high-density neuromorphic circuits.

Abstract Ferroelectric AlScN is a premier candidate for next-generation non-volatile memories and in-memory computing, yet its reliability degradation mechanisms remain unclear. Here, we demonstrate a pronounced polarity dependence in the time-dependent dielectric breakdown (TDDB) statistics of AlScN capacitors and its suppression via plasma oxidation (PO). For as-deposited Al0.7Sc0.3N and Al0.8Sc0.2N, Weibull analysis reveals that the shape parameter (β) is significantly smaller under positive top-electrode bias than under negative bias, suggesting a universal, polarity-sensitive breakdown process. We propose that field-driven migration of near-surface oxygen species modulates defect-network evolution in a polarity-dependent manner. To validate this, the Al0.8Sc0.2N surface was modified by PO. Angle-resolved HAXPES confirmed enhanced near-surface oxidation, and J–V measurements showed reduced leakage current. Crucially, TDDB analysis demonstrated that PO strongly suppresses the polarity dependence of β, consistent with our proposed model. Finally, the voltage acceleration coefficient and 10-year lifetime voltage were evaluated.

The inherent bottleneck of the von Neumann architecture and the limited power budget of edge devices necessitate energy-efficient hardware solutions for artificial intelligence. Memristor-based In-Memory Computing (IMC) has emerged as a promising candidate; however, the high-power consumption of peripheral circuits, particularly Analog-to-Digital Converters (ADCs), and the reliability issues of memristive devices remain significant challenges. In this paper, we propose a hybrid Convolutional Spiking Neural Network (CSNN) architecture designed for resource-constrained edge computing. Our approach integrates digital Non-Leaky Integrate-and-Fire (NLIF) neurons with Knowm Self-Directed Channel (SDC) memristor-based synapses in a 1T1R crossbar array. To maximize power efficiency, we replace conventional high-resolution ADCs with a streamlined readout circuit utilizing a Current Sense Amplifier (CSA) and a 1-bit comparator. Furthermore, we employ an intensity-to-latency temporal coding scheme to minimize spike activity and mitigate device endurance degradation. We validated the proposed system using the MNIST dataset, achieving a classification accuracy of 97.8%, which is comparable to state-of-the-art floating-point SNNs using supervised learning methods. Power analysis confirms that our 1-bit readout method consumes only 18.4% of the energy required by an 8-bit ADC-based approach while maintaining negligible accuracy loss. Additionally, the deterministic single-spike nature of our temporal coding significantly reduces write stress on memristors compared to rate coding. These results demonstrate that the proposed hybrid CSNN offers a robust and energy-efficient solution for neuromorphic edge intelligence.

Real-world traffic is highly dynamic, with pedestrians exhibiting unpredictable movements. Pedestrians' poses are essential cues for predicting their actions, enabling vehicles to respond proactively and reduce accident risks. In autonomous driving, the distance between vehicles and pedestrians is critical, making 3D human pose estimation crucial. In this context, pedestrian pose estimation has been actively studied, and recently, light detection and ranging (LiDAR) sensors have attracted attention due to their accurate 3D depth information and privacy benefits. However, existing LiDAR-based 3D pose estimation methods mainly process 3D data directly, requiring high computational cost and memory. In this paper, we propose a lightweight LiDAR-based 3D human pose estimation method specifically designed for deployment in autonomous driving systems. Unlike conventional 3D direct processing methods, our approach strategically reduces computational complexity by projecting point clouds into 2D depth images and leveraging a lightweight MoveNet, followed by efficient 3D lifting. Furthermore, we introduce a self-occlusion correction algorithm to improve robustness under side-view and bending poses, where depth-based projections often suffer from distortion. Experimental results on benchmark datasets demonstrate that the proposed method achieves competitive pose estimation accuracy while substantially improving efficiency, highlighting its practicality and scalability for real-time autonomous vehicle applications.

Diffusion models have emerged as the state-of-the-art generative paradigm, surpassing GANs in synthesizing high-fidelity images, videos, and audio. However, their reliance on iterative denoising processes imposes substantial computational burdens and memory overheads, creating a significant barrier to their deployment on resource-constrained edge devices. Unlike existing surveys that broadly cover general methodologies, this paper provides a focused review with a specific emphasis on efficient and lightweight diffusion models. We systematically analyze the trade-offs between generation quality and computational cost, categorizing acceleration techniques into sampling optimization, architectural compression, and knowledge distillation. Furthermore, we explore the integration of diffusion models with emerging architectures (e.g., Mamba) and their evolution towards general-purpose world simulators. This survey aims to provide a roadmap for “Green AI,” bridging the gap between high-end academic research and practical, real-world applications.

A review on selective in-memory computing processors: Potential alternative to AI-driven applications

In recent years, anomaly detection in web applications has become increasingly important for security and reliability. For instance, detecting fraudulent transactions in e-commerce platforms or monitoring user behavior in real-time web dashboards requires immediate response and high accuracy. Traditional deep learning models are difficult to deploy in browsers due to CPU/GPU bottlenecks, limited memory, and stringent real-time latency requirements. Deploying deep learning models directly in the browser is challenging due to limited computational resources and memory constraints. To address these challenges, we propose DAPQ-AD, a Dynamic-Aware Pruning-Quantization compression algorithm optimized for WebAssembly execution. Unlike conventional static compression methods, DAPQ-AD not only dynamically adjusts pruning rates and quantization levels based on the characteristics of the input data, but it also adapts to varying input noise, preserves critical features for accurate anomaly detection, and reduces inference latency compared to static approaches. Extensive experiments demonstrate that our method significantly reduces model size and inference latency while maintaining high anomaly detection performance in browser environments. This approach enables lightweight, real-time anomaly detection directly on client-side web applications without compromising accuracy.

The deployment of transformer-based language models on resource-constrained edge devices presents fundamental challenges in computational efficiency and memory utilization. We introduce SQ-LoRA (Stable-rank Quantized Low-Rank Adaptation), a theoretically grounded compression framework that achieves unprecedented efficiency through the synergistic integration of adaptive low-rank decomposition, hardware-accelerated structured sparsity, and intelligent hybrid quantization. Our primary contribution establishes the first rigorous mathematical connection between the matrix stable rank and optimal LoRA rank selection, formalized in Theorem I, which provides bounded approximation guarantees. SQ-LoRA implements: (1) adaptive rank allocation via stable-rank analysis to automatically determine layer-wise compression ratios; (2) 4:8 structured sparsity patterns, enabling 2× hardware acceleration on modern edge processors; and (3) a three-tier quantization scheme that combines 4-bit NormalFloat storage with selective 3-bit/8-bit precision to preserve outliers. A comprehensive evaluation on four diverse natural language processing (NLP) benchmarks demonstrates that SQ-LoRA achieves a 320 MB memory footprint (96.7% reduction) and a 10 ms inference latency (91.7% improvement), and maintains 82.0% average accuracy (within 0.15% of the full model). Statistical significance testing (p < 0.001) confirms its superiority over state-of-the-art methods. This framework enables the deployment of sophisticated language models on devices with 2 GB of RAM, advancing practical edge-AI applications.

Abstract Analog in-memory computing (AIMC) offers a promising solution to the von Neumann bottleneck. However, deploying transformer models on AIMC remains challenging due to their inherent need for flexibility and adaptability across diverse tasks. For the benefits of AIMC to be fully realized, weights of static vector-matrix multiplications must be mapped and programmed to analog devices in a weight-stationary manner. This poses two challenges for adapting a base network to hardware and downstream tasks: (i) conventional analog hardware-aware (AHWA) training requires retraining the entire model, and (ii) reprogramming analog devices is both time- and energy-intensive. To address these issues, we propose AHWA low-rank adaptation (AHWA-LoRA) training, a novel approach for efficiently adapting transformers to AIMC hardware. AHWA-LoRA training keeps the analog weights fixed as meta-weights and introduces lightweight external LoRA modules for both hardware and task adaptation. We validate AHWA-LoRA training on SQuAD v1.1 and the GLUE benchmark, demonstrate its scalability to larger models, and show its effectiveness in instruction tuning and reinforcement learning. We further evaluate a practical deployment scenario that balances AIMC tile latency with digital LoRA processing using optimized pipeline strategies, with RISC-V-based programmable multi-core accelerators. This hybrid architecture achieves efficient transformer inference with only a 4% per-layer overhead compared to a fully AIMC implementation.

Many quantum networking applications require efficient photonic interfaces to quantum memories which can be produced at scale and with high yield. Synthetic diamond offers unique potential for the implementation of this technology as it hosts color centers which retain coherent optical interfaces and long spin coherence times in nanophotonic structures. Here, we report a technique enabling wafer-scale processing of thin-film diamond that combines ion implantation and membrane liftoff, high-quality overgrowth, targeted color center implantation, and serial, high-throughput thermocompression bonding with yields approaching unity. The deterministic deposition of thin diamond membranes onto semiconductor substrates facilitates consistent integration of photonic crystal cavities with silicon-vacancy (SiV) quantum memories. We demonstrate reliable, strong coupling of SiVs to photons with cooperativities approaching 50. Furthermore, we show that photonic crystal cavities can be reliably fabricated across several membranes bonded to the same handling chip. Our platform enables modular fabrication where the photonic layer can be integrated with functionalized substrates featuring electronic control lines such as coplanar waveguides for microwave delivery. Finally, we implement passive optical packaging with sub-decibel insertion loss. Together, these advances pave the way to the scalable assembly of optically addressable quantum memory arrays which are a key building block for modular photonic quantum interconnects.

Introduction. Currently the most widely used digital signal processing methods are those using specialized digital computers, which utilize analog-to-digital conversion of not only the input signals but also the weighting coefficients of the digital filters. This conversion results in quantization noise in the input signals, which reduces the efficiency of the specialized computer. The operating algorithms of these specialized computers are determined by the discrete transfer functions of the digital filters. The transfer function of a specific digital filter is determined by a set of weighting coefficients, which, like the input signals, are quantized by level and loaded into the computer memory. When quantizing the weighting coefficients, errors arise, the magnitude of which is determined by the quantization step. Weighting coefficient quantization errors inevitably affect the frequency properties of digital filters. Objective. To evaluate the influence of the weighting coefficient quantization step on the frequency characteristics of digital low-pass and high-pass filters, band-pass and notch filters of various orders. Method. The study utilized the bilinear z-transformation of the frequency transfer functions of continuous analog filters. Results. Transfer functions in the z-plane of digital low-pass and high-pass filters, band-pass and notch filters of various orders were obtained. Distortions in the frequency transfer functions of digital filters were calculated as a function of the weighting coefficient quantization step. Conclusions. Quantization of weighting coefficients leads to inevitable distortions in the frequency transfer functions of digital filters, the extent of which is determined by the quantization step size. The influence of the quantization step on the resulting distortions in the frequency transfer functions of digital filters must be taken into account when designing digital computers, specifically when selecting the number of binary digits and the quantization step size of a specialized computer. The results of this work will be of great use to designers of digital signal processing devices.

Memristor-based in-memory computing has emerged as a promising paradigm to overcome the constraints of the von Neumann bottleneck and the memory wall by enabling fully parallelisable and energy-efficient vector-matrix multiplications. We investigate the effect of nonlinear, memristor-driven weight updates on the convergence behaviour of neural networks trained with equilibrium propagation (EqProp). Six memristor models were characterised by their voltage-current hysteresis and integrated into the EBANA framework for evaluation on two benchmark classification tasks. EqProp can achieve robust convergence under nonlinear weight updates, provided that memristors exhibit a sufficiently wide resistance range of at least an order of magnitude.

The increasing demand for information storage makes the development of advanced materials and regulation strategies urgent, integrating low-power consumption with a rapid resistive switching behavior. Perovskite nickelates, leveraging their unique metal-insulator transition, emerge as an ideal material platform for resistive switching applications. However, traditional modulation strategies (such as strain, electric fields, and ionic liquids) remain plagued by energy inefficiency and response hysteresis. Here, we demonstrate a visible light-modulated metal-insulator transition in NdNiO3 photovoltaic heterostructures, achieving 2 orders of magnitude resistivity switching under low-intensity 20 mW·cm-2 (0.2 sun) illumination with transient time. The photoinduced electron doping makes Ni 3d-orbital reconstruction to present the metallic behavior, where its upper Hubbard band broadens and is below the Fermi level. Nevertheless, these charged VO existing in the NdNiO3-δ interlayer would serve as charge recombination centers and severe electron-hole pair quenching, thereby aggravating the insulating behavior. By integrating multilevel resistive switching tunability (changing light intensity or temperature) and high-fidelity state reproducibility, our work establishes NdNiO3 photovoltaic heterostructures to provide a new research platform for low-power optoelectronic memory and neuromorphic computing.

The advent of intelligent fault diagnosis has advanced condition monitoring in industrial machinery. This study develops and evaluates two lightweight convolutional neural networks (CNNs): a 1-D CNN for time-domain vibration signals and a 2-D CNN for continuous wavelet transform (CWT)–based scalogram images in rolling-element bearing fault diagnosis. A key feature of this work is its dual-modality framework that independently examines temporal and time–frequency representations to assess diagnostic accuracy and computational efficiency. Using the Case Western Reserve University (CWRU) dataset and an in-house experimental dataset, both models demonstrate strong generalization under variable conditions. The 1-D CNN achieves 99.67% mean accuracy with significantly lower computation time and memory usage than AlexNet and GoogLeNet, while the 2-D CNN attains 98.74% accuracy with improved interpretability. Performance remains stable across 10 independent runs, with 95% confidence intervals confirming the robustness of both models for future edge-oriented fault diagnosis applications.

Abstract: The swift development of the Internet of Things (IoT) is leading to the development of a multitude of intelligent devices, with profound implementation for security. In addition to their purported security level, IoT devices typically include limited resources, including minimal computational power, limited memory, and restricted battery capacity. Proposed within the context of IoT, lightweight cryptographic primitives aim to balance the trade-off between providing a high level of security and achieving good performance. One of the lightweight cryptography (LWC) algorithms is Ascon. Ascon has been selected as the primary recommendation for lightweight authentication encryption in the final round of The Competition for Authenticated Encryption: Security, Applicability, and Robustness (CAESAR) competition. Within this review, research papers have been explored that showcase diverse methodologies utilized in Ascon hardware implementation. To assess the research papers, the categorization is done according to the hardware design techniques utilized in prior research. This review study analyzes several works, analyzing them based on many factors, including the classification of methodologies employed for hardware implementation design and the evaluation of performance indicators. This review examines the potential areas for improvement by examining the research obstacles highlighted in the current literature, offering suggestions to researchers to enhance their work. After reviewing the conclusion can be made on which hardware implementation design can result in higher performance for lightweight encryption.

This work presents a 6T-SRAM-based in-memory computing (IMC) system fabricated in a 180 nm CMOS technology. A total of 128 integrated polysilicon R2R-DACs for fully analog wordline control and performance analysis are integrated into the system. The proposed architecture enables analog computation directly inside the memory array and introduces a compact 1-bit per-column comparator scheme for energy-efficient classification without requiring ADCs. A dedicated pull-down-dominant SRAM sizing and an analog activation scheme ensure stable analog discharge behavior and precise control of the computation through time-dependent bitline dynamics. The system integrates a complete sensor front-end, which allows real eddy current data to be classified directly on-chip. Measurements demonstrate a performance density of 3.2 TOPS/mm2, a simulated energy efficiency of 45 TOPS/W at 50 MHz, and a measured efficiency of 3.4 TOPS/W at 5 MHz on silicon. The implemented online training mechanism further improves classification accuracy by adapting the SRAM cell states during operation. These results highlight the suitability of the presented IMC architecture for compact, low-power edge intelligence and sensor-driven machine learning applications.