Advanced Micro Devices (Canada)

System-on-chip security architecture is a critical, complex, and time-consuming activity, consuming months of effort. Furthermore, the architectural design can include subtle errors that compromise the security of the entire system. In this paper, we develop a security engine infrastructure, SEnTry , for systematically creating security architectures for protecting SoC designs against a variety of security subversions. SEnTry provides a plug-and-play, configurable subsystem composed of custom IPs that can be integrated into the platform to derive different security primitives. We develop an instance of SEnTry for supply-chain attacks. We discuss the spectrum of challenges involved in developing a unified architecture for systematic protection against the variety of attacks involved and the SEnTry approach to addressing them. We provide several case studies to demonstrate SEnTry design and perform extensive experiments to evaluate its overhead on multiple ASIC technologies. Our experiments suggest that SEnTry incurs minimal overhead in area and power consumption.

High-performance microprocessors and accelerators, integral to data centers, require power delivery networks capable of managing higher currents and power densities while operating at lower voltages. The surge in generative AI applications is reshaping the landscape of semiconductor hardware, necessitating advanced power delivery solutions to meet escalating demands for efficiency and performance. As AI workloads intensify, traditional power delivery methods struggle to provide the necessary energy without compromising spatial constraints on circuit boards. This paper addresses the critical challenges posed by embedded passive components, specifically capacitors and inductors, while demonstrating an embedded voltage regulation (eVR) STile™. We introduce an innovative approach that leverages embedded passive technology to enhance power efficiency. This paper will demonstrate the integration of capacitors and inductors directly into the package substrate to enable for the first time and subsequently vertical power delivery directly into the package substrate. This demonstration of highly integrated passive components serves to optimize the power delivery network through reduction in the power path length as well as leveraging high performance passive components. By addressing these power delivery challenges, we pave the way for the next generation of semiconductor hardware tailored to the demands of next generation AI applications. Ensuring optimal power signal integrity is vital for maintaining stable voltage delivery across a wide frequency range. A standard design methodology focuses on minimizing the impedance seen by the load’s input nodes, thereby reducing voltage ripple and droop during transient events. STile technology improves performance by embedding high capacitance density capacitors close to the load and combining them with complimentary inductors to, significantly reduce parasitics and optimize space for both VPD and embedded voltage regulation (eVR) solutions. This paper will demonstrate the ability to integrate these passive components specifically designed to support integrated voltage regulation inside of the package. This paper will show configurations of passive components that support a variety of different domains for traditional high performance computing die. This paper will also demonstrate the superior performance capable of being achieved as compared to traditional power delivery network’s. These traditional power delivery networks perform the voltage conversion from 48V to POL (Point of Load) voltages in discrete and bulky modules on the periphery of the printed circuit board. These modules combine the use of inductors, capacitors and actives however, are significantly far away from the load that efficiency of the network becomes a problem. To minimize I²R losses, efficient power delivery demands higher voltages and low current levels at the package substrate level. While conventional power regulator topologies typically utilize inductors to achieve high conversion efficiencies, integrating inductors onto the die can complicate design and elevate costs. The STile technology provides a groundbreaking solution by enabling the co-location of inductors and capacitors within a customizable three-terminal LC passive module (patent pending) embedded in the core substrate. This integration allows for precise alignment with processor power domains, significantly reducing the need for lateral metal routing. Additionally, the flexible layout of the LC passive modules supports multiple power domains, facilitating interleaved multiphase outputs and innovative configurations such as sharing output capacitors among several inductors. By addressing these design challenges, eVR STile technology significantly enhances power delivery efficiency while meeting the stringent demands of next-generation semiconductor applications. This paper emphasizes the development of advanced, highly integrated capacitor and inductor solutions that deliver superior performance for next-generation power delivery systems. By leveraging STile technology, we illustrate how embedding capacitors and inductors within the substrate not only enhances power signal integrity and minimizes parasitics but also optimizes space for embedded voltage regulation (eVR). This innovative platform enables the creation of custom eVR designs tailored to specific application requirements, significantly improving efficiency in high-performance computing environments. Through our findings, we highlight the transformative potential of these embedded passive components in addressing the power delivery challenges faced by next generation artificial intelligence chips.

Deep Neural Networks (DNNs) are crucial for applications like autonomous driving, augmented reality, and mixed reality. Growing concerns about latency and privacy increasingly require deploying task-specific networks on mobile and edge devices. Extensive research focuses on accelerating DNNs while preserving output quality, particularly through model adjustments tailored for resource-limited devices [1-5].

Stardust load emulator (SDLE) is AMD’s proprietary tool that is used to validate voltage regulator (VR) power delivery (PD) design on motherboards that are dedicated to AMD’s CPU. This paper proposed a new full system simulation methodology to incorporate three major segments of design into a single framework to evaluate system performance. The simulation and lab measurement data are highly correlated with less than 3% discrepancy.

Deep learning models have grown increasingly complex, with input data sizes scaling accordingly. Despite substantial advances in specialized deep learning hardware, data loading continues to be a major bottleneck that limits training and inference speed. To address this challenge, we propose training models directly on encoded JPEG features, reducing the computational overhead associated with full JPEG decoding and significantly improving data loading efficiency. While prior works have focused on recognition tasks, we investigate the effectiveness of this approach for the restoration task of single-image super-resolution (SISR). We present a lightweight super-resolution pipeline that operates on JPEG discrete cosine transform (DCT) coefficients in the frequency domain. Our pipeline achieves a 2.6 x speedup in data loading and a 2.5 x speedup in training, while preserving visual quality comparable to standard SISR approaches.

Up to the current fall patterns that started at the end of 2021, the Chinese real estate market has developed at such a rapid pace over the course of the previous few decades. Investors and the government have found it more difficult to accurately forecast future property values as a consequence of this challenge. It is because of the current status of the economy that this has come about. For the purpose of this study, we use Gaussian process regressions using a wide range of kernels and basis functions to investigate the monthly residential property prices in Ningbo City, which is located in Zhejiang Province, China. The time period covered by this study is from May 2011 to July 2024. Estimated models are used in our forecasting endeavors. These models are trained using a mix of cross-validation and Bayesian optimizations. The models that were developed were effective in accurately forecasting the prices that would be seen out of sample from December 2021 to July 2024. With a relative root mean square error of 0.1626 percent, these models may be considered accurate. It is possible that our results might be utilized on their own or in conjunction with further forecasts in order to construct hypotheses about variations in the values of residential real estate and to carry out additional policy research.

Terahertz (THz) spectroscopy can obtain characteristic fingerprint spectra by detecting the structural vibrations of molecules. Nanophotonic enhancement and subwavelength field confinement have expanded the application scope of this technology. However, current methods still require complex spectroscopic equipment and face obstacles in the trace analysis of analytes and broadband detection. Here, we introduce a novel metasurface design approach to detect the broadband absorption spectra of molecules, which combines the simplest detection method (transmission metasurface chipset) with the chemical specificity of THz spectroscopy. Specifically, we designed a metasurface chipset based on Fano resonance, capable of providing frequency-selective spectra and surface-sensitive resonances between 0.18 and 1.20 THz. We used this method to detect distinct absorption signatures of different interacting analytes, including l-tyrosine (5 and 10 mg/mL) and bovine hemoglobin. By combining the molecular absorption spectra with the transmission spectra of each metasurface chip, broadband detection was achieved through the design of the metasurface chipset, paving the way for the field-deployable applications of miniature THz spectroscopy devices.

Adoption of precision agriculture in developing countries remains low due to lack of affordable technologies, and the benefits cannot be sufficient to justify the costs. In this context, a cost-effective navigation method can be implemented to enable autonomous driving in agricultural fields using only low-cost camera and conventional GPS. This method potentially enables agricultural autonomous machines to precisely navigate between crop rows and avoid obstacles in real-time operation. Such method can be helpful for small farmers to do cost-effective tasks of weeding and applying chemicals. This work aims to develop a low-cost vision navigation system based on a low-cost RGB camera vision system as an alternative to use of a precise RTK GPS system. By implementing an image processing method based on RANSAC algorithm, the tests showed the ability of implementing an accurate detection method of crop lines and boundary limits as keys of an efficient driving system. This vision system can be improved using repetitive training of the imaging process and taking advantage of recent advances in the field of machine learning. Development of this cost-effective autonomous navigation system is potentially of great interest for small farming systems to operate machines between crop rows and carry out agricultural tasks.

Modern GPUs require power optimization to improve performance and reduce energy use, especially in portable, battery-powered devices with strict power limits. These systems often throttle frequencies below what the minimum voltage (Vmin) can support, resulting in inefficient per-watt performance. Graphics (GFX) duty cycle scaling (DCS) addresses this by alternating between the GFX ON (at Fmax@Vmin) and GFX OFF states, reducing the average power consumption.

In the labyrinthine landscape of macroeconomic data, where subtle anomalies can herald significant economic shifts, this paper proposes a novel hybrid framework for their accurate and timely detection. The framework effectively combines an Autoregressive Integrated Moving Average (ARIMA) model for solid baseline forecasting with Long Short-Term Memory (LSTM) networks and a variational autoencoder that incorporates LSTM layers (VAE-LSTM) to capture complex residual patterns analysis. A unique dynamic weighting method, which includes temporal smoothing and differences in macroeconomic states, adaptively fuses the outputs of these models, leveraging their strengths across diverse economic scenarios. The proposed hybrid framework’s efficacy was evaluated on a dataset of 348 macroeconomic indicators from Brazil, Russia, India, China, and South Africa (BRICS) nations, covering 1970 to 2020. Empirical results show the framework outperforms other state-of-the-art (SoTA) methods: ARIMA, LSTM, VAE-LSTM, Autoencoder (AE), Isolation Forest (IF) and One-Class Support Vector Machine (OCSVM) achieving an F1-score of 0.915 with AUC of 0.926 and PR-AUC of 0.839. Furthermore, sensitivity analysis substantiates the framework’s robustness across different weighting configurations, maintaining consistent F1-scores between 0.887 and 0.915. The proposed framework offers a robust and adaptive approach to anomaly detection in complex macroeconomic time series, with potential applications in risk management, policy formulation, and economic forecasting.