Analog Devices (Ireland)

The comparator is a vital block in any integrated DC-DC power converter for both control and protection functions. Monolithic GaN HEMT power converters offer superior power switching performance with lower on-resistances and capacitances, however they suffer from poor analog performance due to their lack of complementary devices and poor device mismatch as well as a limited range of devices. This paper presents the design of a depletion-mode input pair based regenerative comparator monolithically integrated on a GaN-on-Si process. This paper aims to investigate and demonstrate the input-referred offset performance of such a comparator. The structure delivers a transistor level simulated 1-σ input-referred offset of 3.6 mV without the use of any offset cancellation techniques. It achieves rising and falling propagation delays of 29 ns and 22 ns, respectively with a 100 mV overdrive and 1 pF load capacitance. The comparator occupies an area of approximately 0.055 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and has a quiescent current consumption of 63 μA.

This paper presents a method for correcting nonlinearities in voltage-controlled oscillator (VCO) based analog-to-digital converters (ADCs). The proposed approach utilizes a simple digital logic circuit, three single-stage transistor-based circuits, and four switches to enhance the linearity of the VCO tuning curve. The prototype is designed in 65-nm CMOS process with a supply voltage of 1.2 V and measurements have demonstrated that the pseudo-differential VCO-based ADC achieves 2.5-bit improvement in the Effective Number of Bits (ENOB), with only marginal increases of 5.2% and 9% in total power and area, respectively.

This paper presents a review of CMOS circuit trends for biomedical applications. Biosignals are explored in relation to their bandwidth, providing insights into the circuit set requirements for effective signal conditioning. The need for such conditioning arises particularly when integrating very low-frequency poles and zeros into silicon. We analyze relevant proposals from the open literature, specifically focusing on in-field applications where both Power Supply Rejection Ratio (PSRR) and Common-Mode Rejection Ratio (CMRR) must exceed -70dB and 80dB, respectively.

Fractional-N PLLs are plagued by spurs that result from interaction between the shaped quantization noise introduced by the controller of the feedback divider and non-linearities in the loop. In addition to fixed spurs associated with the fractional input to the divider controller, fractional-N PLLs can also exhibit (i) fixed spurs, whose positions depend on the initial phase setting, and (ii) moving or “wandering” spurs. These become important in applications such as phased arrays that require phase offsets between multiple PLLs and radar applications where wandering spurs can be wrongly interpreted as targets. The divider controller in a fractional-N PLL is commonly implemented as a digital delta-sigma modulator (DΔΣM). The principal source of non-linearity is a time-interval measurement subsystem (TIMS), whose output is a measure of the time interval between the edges of the reference and feedback-divider signals. In a charge-pump (CP) PLL (CP-PLL), the TIMS comprises a phase frequency detector (PFD) and a CP and is typically characterized by a smooth non-linearity. In an all-digital PLL (ADPLL), the TIMS is usually a time-to-digital converter (TDC) that introduces a quantization non-linearity. In bangbang (BB) BB PLLs, the ref and div edges are usually brought into closer alignment using a multibit digital-to-time converter (DTC) before measuring the difference between them. The DTC introduces an additional quantization mismatch and other non-linearities.

There is an increasing demand for high-performance, low-cost, small footprint, reliable silicon-based voltage references. A circuit architecture incorporating all the above criteria was developed and presented in [1], [2], [3]. One major architectural performance limitation common to all, was their ability to mitigate only the 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> order temperature dependency of the Zener Diode used to generate the voltage reference. While incorporating the learning from [4] and [5], this paper proposes a novel compensation technique, capable of correcting independently both the 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sup> t, and the 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> order coefficients of the temperature dependency associated with any Zener-based voltage reference with thermally uncompensated substrate, thus allowing the trade-off between noise and power without sacrificing temperature stability. The circuit is currently in full prototype development stage. Throughout all process corners, a temperature coefficient of maximum 0.7ppm/°C was simulated for the proposed circuit.

Apart from the well-known nonlinearity-induced fixed spurs, a DDSM divider-based fractional- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$N$</tex> frequency synthesizer can manifest spurs with time-varying frequency offsets from the carrier; these are called wandering spurs. This paper presents experimental results for a 4.9 GHz CP-PLL fractional- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$N$</tex> PLL featuring a modified MASH-based divider controller that implements wandering spur suppression. The synthesizer achieves a 20 dB reduction in the spectral envelope of the short-term output phase noise spectrum when compared to the standard MASH DDSM divider controller.

Document layout analysis plays an important role in the area of Document Understanding. It is responsible for identifying and classifying the different components of digital documents. Currently, there is no universal algorithm that fits all types of digital documents. This work presents a novel approach for identifying tables, figures, isolated equations, and text regions in scientific papers using deep learning and computer vision techniques. Our proposed approach is a three-stage system: (i) obtaining the spectrograms of the horizontal and vertical intensity histograms of segmented regions of interest. (ii) labeling segmented regions of interest into text, table, and figures using a deep convolutional neural network classifier. (iii) identifying isolated equations in text regions using Bag of Visual Words (BOVW) with Zernike moments. We built a new dataset composed of 11007 papers to perform the experiments, using two common segmentation metrics to evaluate our model: (1) Adjusted Rand Index (ARI) and (2) Variation of Information (VI). The proposed document layout analysis system reached an overall accuracy of 96.2685%, outperforming prior art with a less computational cost.

The isolation behaviour of polyimide thin films has been studied. Properties such as DC conductivity and the threshold electrical fields were obtained through a steady state current measurement under an applied voltage across a metal-insulator-metal capacitor. An inverse relationship has been found between the curing temperature and threshold electric field that would be applied to the structure. The results correlate with high voltage endurance life-time curves for digital isolators processed at different temperatures.

Analog FIR filtering is proposed to improve the performance of a single stage g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -C channel selection filter for ultra low power Internet-of-Things receivers. The transconductor is implemented as a digital-to-analog converter; allowing a varying transconductance in time, which results in a very sharp FIR filter. The filter is manufactured in 22-nm FDSOI and has a core area of 0.09 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It consumes 92 μW from a 700-mV supply and achieves f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-60</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dB</sub> /f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dB</sub> = 3.8. The filter has 31.5 dB gain, out-of-band OIP3 of 28 dBm and output referred 1-dB compression point of 3.7 dBm. The filter bandwidth is tunable from 0.06 to 3.4 MHz.