Pushing the Limits of kT/C Noise in Delta-Sigma Modulators

The envelope pulse-width modulation (EPWM) transmitter has been studied to address the power efficiency issue on the linear amplification of OFDM signals. However, the delta- sigma (Delta-Sigma) modulator in the EPWM transmitter generates quantization noise that degrades signal quality. In this paper, OFDM in-band noise characteristics of EPWM transmitters are analyzed for first and second order Delta-Sigma modulators. Distortion noise power due to envelope clipping of OFDM signals is also analyzed. The combined effects of noise and distortion on the error vector magnitude (EVM) and adjacent channel leakage power ratio (ACLR) are examined. Simulations to validate the total performance were performed using the IEEE 802.11a OFDM signal. Results showed good agreement with analytical results considering a linear-approximation gain for the 1-bit quantizer in Delta-Sigma modulators. The first order EPWM transmitter provides slightly better EVM and ACLR values than second order EPWM transmitters, since the effective quantizer gain of second order Delta-Sigma modulators is smaller, that limits the noise- shaping capability of Delta-Sigma modulators. A 0.1% clipping probability for a first order EPWM transmitter with an oversampling ratio of 32 and a three-pole Butterworth bandpass filter gives an EVM of 1.8% and ACLR of-37.9 dB.

This Letter proposes a probabilistic shaping delta-sigma modulation technique. By performing delta-sigma modulation on the probability shaping signal at the transmitting end, under the same transmit power and the same net bit rate, the delta-sigma modulation signal based on probability shaping can obtain better anti-noise capability than the delta-sigma modulation signal only. Under the same information entropy conditions, the bit error rate performance of the PS-based 131072QAM signal modulated by delta-sigma modulation is better than that of the ordinary 65536QAM signal using the delta-sigma modulation scheme, and lower than that of soft decision-forward error correction (4 × 10-2).

Sigma delta modulation is a popular technique for high-resolution analog-to-digital conversion and digital-to-analog conversion. We investigate chaotic phenomena in multibit first-order sigma-delta modulators. Particular attention is placed on the occurrence of periodic orbits or limit cycles. These may result in idle tones audible to the listener when sigma-delta modulation is used for audio signal processing. One suggested method of eliminating idle tones is the operation of a sigma delta modulator in the chaotic regime. Unfortunately, chaotic modulation of a first order sigma delta modulator is a poor system for signal processing. We show that minor variations on a traditional first order sigma-delta modulator, together with a multibit implementation, may be used to produce an effective, stable chaotic modulator that accurately encodes the input and helps remove the presence of idle tones. (c) 2001 American Institute of Physics.

A digital adaptive calibration technique to linearize sigma-delta (ΣΔ) modulators based on an output-referred distortion analysis of discrete-time integrators (DTIs) is presented. A sequential power series (a special form of Volterra series) is found sufficient to model the nonlinear memory errors in a DTI, which entails the application of adaptive polynomial transversal filtering for error correction of the modulator. Error-parameter identification is accomplished by correlating various moments of the digital output with a 1-bit pseudorandom noise, which is injected into the analog input of each DTI of the modulator. Simulations demonstrate the effectiveness of the technique in compensating the signal-dependent errors of first- and second-order ΣΔ modulators.

Sigma-Delta modulators (SDMs) are capable of shaping the quantization noise out of a specific frequency band defined by their noise transfer function (NTF). A single-bit output SDM pose further advantages in applications that would typically require a multi-bit DAC, since then only a single-bit DAC is required, which is much easier to design and is inherently linear in comparison to a multi-bit one. Look-ahead SDMs have been proposed to enhance the signal-to-noise-and-distortion-ratio (SNDR) and the output bandwidth of conventional single-bit SDMs. Multi-Step Look-Ahead sigma-delta modulators (MSLA SDMs) further reduce the hardware complexity required for the implementation of typical look-ahead SDMs while maintaining their performance advantages. In this work the architecture and the benefits of the MSLA SDMs are showcased. Finally the advantages of the MSLA SDMs over single-bit conventional ones are demonstrated and several hardware implementation choices for design optimization are discussed.

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

With the development of science and technology, Sigma-Delta (∑-A) ADCs are widely used in various fields of electronics with their flexible advantages. As an essential component of a Sigma-Delta ADC, digital filters directly and significantly impact the ADC's accuracy, delay, and power consumption. This paper presents a multistage digital filter for 18-bit ∑-A ADCs; the filter uses a cascade of multiple filters, including cosine-like (CL), cascaded integral comb (CIC), interpolated second-order polynomial (ISOP), and half-band (HB) filters, to enhance the ADC's accuracy. The filter's order and downsampling multiplier are designed using canonical signed digit (CSD) and common subexpression (CSE) to reduce hardware resource consumption and improve computational performance. The ADC is synthesized using 0.18 µm CMOS technology, achieving an output SNDR of 96.26 dB, ENOB of 15.73 bits, total power of 518.35 uW, and a Digital filter power of 82.93 uW, which effectively reduces the power consumption while improving the accuracy.

Multi-carrier systems such as Orthogonal Frequency Division Multiplexing (OFDM) require linear amplification and have low power efficiency because of high peak-to-average power ratio (PAPR). In an Envelope Pulse-Width Modulation (EPWM) transmitter, the envelope component of a linear modulation wave is converted to a PWM signal by a delta-sigma (Delta-Sigma) modulator while the phase component modulates the carrier signal. The distortion-free amplitude multiplexing of the PWM and PM signals enables the power amplifier to achieve maximum power efficiency. In this paper, EPWM transmitter characteristics such as noise power spectral density and SNR will be analyzed. The application of the EPWM transmitter to OFDM signals will also be explored. From the simulation results, the Delta-Sigma modulator with an oversampling ratio of 32 provides sufficient in-band SNR and adjacent channel power ratio required for the IEEE 802.11a OFDM system.

The fact that VCO-ADCs produce noise-shaped quantization noise suggests that a link between frequency modulation and Sigma-Delta modulation should exist. The connection between a VCO-ADC and a first-order Sigma-Delta modulator has been already explained using Pulse Frequency Modulation. In this article, we attempt to extend this explanation to a generic Sigma-Delta modulator. We show that the link between Sigma-Delta modulation and Pulse Frequency Modulation relies in a sampling invariance property that defines the equivalence between both entities. This equivalence property, allows to go beyond the white quantization noise model of a Sigma-Delta modulator, revealing the origin of some nonlinear phenomena. We first predict spurious tones which cannot be explained by circuit non linearity. Multi-bit and single-bit modulators are shown to belong to a same generic class of systems. Finally, quantizer overload is analyzed using our model. The results are applied to Continuous-Time Sigma-Delta modulators of orders one, two and three and then extended to a generic case.

A delta-sigma modulator (DSM) is proposed for the direct connection to micro-electro-mechanical systems (MEMS) microphone. To reduce power, both the DAC reference voltage (VREF) and the DSM supply voltage (VDD) are reduced to 700 mV by limiting the maximum linear acoustic input range to 110 dB SPL (sound pressure level). For the low VDD operation, the switched capacitor (SC) integrators of DSM employ CMOS inverters as amplifiers. A unity-gain buffer compensates the pole error of the SC integrator; it reduces chip area by replacing the auto-zero capacitor of conventional inverter-based SC integrator. Compared to the conventional integrator, the integrator of this brief reduces the pole error from 0.3% to 0.06%, reduces the chip area and the power by 32.4% and 24.8%, respectively. The 3rd order DSM in a 65 nm CMOS process was measured to have Walden-figure of merit (FoMw) 89.3fJ/step, dynamic range (DR) 90.1 dB, signal-to-noise ratio (SNR) 87.2 dB, signal-to-noise and distortion ratio (SNDR) 86.4 dB, and power 122 uW at 10 MHz clock frequency (Fs).

The chapter presents a conception of a power electronics inverter based on a modified sigma-delta modulator (SDM) being used in the inverter’s control block. The proposed modulator includes a comparator with dynamic hysteresis instead of a latched comparator, which is typically used in single-bit SDMs. Thanks to this feature, the resolution of the SDM output bit stream is, theoretically, unlimited. As a result, the value of the THD of an inverter output voltage (current) is much lower than that of a typical SDM solution. This benefit is not offset by an increase in the system’s complexity. Moreover, the control system is simpler than in the case of a conventional inverter. Due to the very high frequency of an SDM output bit stream, in a power stage of the inverter, the gallium-nitride (GaN)-based E-HEMTs (Enhancement mode High Speed Mobility Transistors) are implemented. However, in the case of a lower value of an inverter output power, an Si-based device is still the proper choice. In the chapter, the inverter control circuit basics, the results of simulation experiments and a possible practical arrangement of this one as a voltage-controlled voltage source (VCVS) are presented.

The parallelism between a first-order sigma-delta modulator and a VCO-based ADC allows to calculate the DFT of the sigma delta sequence using Pulse Frequency Modulation theory. This paper exploits this parallelism to propose a more general model that links continuous time sigma delta modulators of an arbitrary order with Pulse Frequency Modulators. This novel point of view also predicts the spectral contents of a sigma delta encoded sequence beyond the white quantization noise model. The quantization noise can be split in two components, a deterministic one representing the carrier harmonic sidebands of a Pulse Frequency Encoded signal and a noise shaped pseudorandom signal representing the sampling operation. We seize these findings to propose a conjecture on the stability of a sigma delta modulator.

Although delta-sigma modulators are widely used for low to moderate rate analog-to-digital conversion, the time over-sampling requirement has limited their application to higher rate converters. This paper presents an architecture wherein multiple delta-sigma modulators are combined with time interlacing. Instead, the system achieves the effect of over-sampling from the multiplicity of delta-sigma modulators. For a system containing M Lth order delta-sigma modulators, approximately L bits of accuracy are gained for every doubling of M. A major benefit of the architecture is that it retains much of robustness of the individual delta-sigma modulators to non-ideal circuit behavior. As a result, the architecture offers the potential of integrating high-precision, high-speed ADC together with digital signal processing functions using VLSI processes optimized for digital circuitry. Because of parallelism, the performance of the architecture is hugely degraded by channel mismatches. A digital technique is used to overcome this problem. The paper presents the general architecture and provides a performance analysis closely supported by computer simulations.

A self-adaptive Sigma-Delta modulator, which offers opportunity to simplify the process of tuning parameters and further improve the noise performance, is presented in this paper. Traditional Sigma-Delta modulator mainly focused on using a 2nd order sensing element to improve the SNR, whereas this paper presents a 5th order Sigma-Delta modulator to obtain higher SNR. Specifically, an additional 3rd order digital loop integrator is inserted between the AFE and the quantizer, which increases overall loop order to produce much higher SNR for Sigma-Delta modulator and the parameters of the 3rd order digital loop integrator are optimized by swarm intelligent algorithm. Simulation results with respect to the proposed 5th order Sigma-Delta modulator, SNR >122 dB and the noise floor under -170dB are obtained in frequency range of [5-150Hz]. In further simulation, the robustness of the proposed 5th order Sigma-Delta modulator is analyzed.

The rapid scaling in modern CMOS technology has motivated the researchers to design new analog-to-digital converter (ADC) architectures that can properly work in lower supply voltage. An exchanging the data quantization procedure from the amplitude to the time domain, can be a promising alternative well adapt with the technology scaling. This paper is going to review the recent development in time-based noise-shaping ADCs, so-called as time-based sigma-delta modulators. Two of the most important architectures named as voltage-controlled oscillator (VCO) -based and time-to-digital (TDC) -based sigma-delta modulators (SDMs) are selected to be reviewed in this paper. The intrinsic advantages and limitations of the these structures are briefly explored. To confirm the effectiveness of the time-mode sigma-delta modulators, a TDC-based continuous-time sigma-delta modulator is proposed as an example and the related simulation results performed in MATLAB are illustrated. The simulation results show that the proposed modulator achieves a dynamic range of 67 dB over 30 MHz with the loop filter of order 2. The proposed TDC-based sigma-delta modulator shows the superiority of the time quantization approach in designing the wideband and less complex continuous-time SDMs.