EV Group (Austria)

Summary A 25‐year‐old Icelandic mare diagnosed with bilateral temporohyoid‐osteoarthropathy, moderate pharyngeal instability and bilateral laryngeal paralysis was presented because of intermittent stridor and dyspnoea worsening during exercise. As a previous ceratohyoidectomy had not improved these symptoms substantially, a permanent tracheostomy was performed. After development of a surgical site infection and dehiscence followed by revision, the final stoma collapsed at times, especially during exercise, resulting in respiratory distress. To stabilise the stoma, a tracheotomy tube was constructed with Autodesk Fusion® and printed from TPU‐95 material with an Ultimaker® S5 3D‐printer. The parametric design allowed fast adaptation in size, shape and stiffness as wound healing progressed. Precision adjustments of size and shape were conducted on an ambulatory basis over a period of several weeks. Intermittently placed by the owner, the device prevented stoma collapse during exercise and was well tolerated by the horse without causing irritation or pressure sores. It was easy to clean, soft but robust and could be replaced and adapted easily. The present case suggests that a 3D‐printed tracheotomy tube is an affordable and effective measure to stabilise a permanent tracheostoma and resulted in improved airway function of the affected horse.

As performance gains from 2D scaling and innovation slows, wafer-level hybrid bonding has become a key enabler for 3D scaling and heterogenous integration. Over the last decade, the industry has seen aggressive shrinking of wafer-to-wafer (W2W) bond pitches from 4 μm to 200 nm to meet the demands of next generation device connectivity requirements. Such aggressive pitch and Cu density scaling necessitates innovations in materials and process equipment (films, etch, treatments, CMP), bonding equipment and thoughtful Design Technology CoOptimization (DTCO) to ensure precise dimensional control and signal reliability. This approach enabled a first successful demonstration of W2W hybrid bonding at a bond pitch of 100 nm through careful design, materials and module co-optimization.

The UHD FO WLP design that will be required for future HPC and AI devices places stringent requirements on the lithographic patterning of the RDL and VIA. The patterning technology must be sufficiently flexible to accommodate multiple design modifications and provide rapid tape out support for the accelerated development of innovative semiconductor devices. The material must possess enhanced dielectric properties, enabling the patterning of the bottom via profiles with a profile less the 5 µm, with the film thickness remaining at 5 µm, and proving the sustainable development of materials. The combination of the patterning with the recently developed digital lithography system and high-resolution polyimide dielectric ensures that the technology, materials, and processes meet the requisite advanced packaging standards.

Surface pattern formation of Smart Cut™ silicon-on-insulator (SOI) substrates is investigated using a new process derived from this technology. The local control of SOI surface roughness is achieved by using hetero-temperature surface activated bonding to introduce locally bespoke shear stresses into bonded silicon wafers. The finite element method is used to back up experimental measurements of these large deformations to determine the amount of shear stresses introduced into the structure, and to determine its impact on the fracture mechanism.

Direct wafer bonding, named also fusion wafer bonding, is based on the formation of molecular bonds between the two surfaces placed in contact. By the initiation of the contact between the two surfaces the bond is self-propagating: at the initiation point a bondwave is generated, which propagates free until the entire surfaces are in contact (bonded). The dynamic of the bondwave propagation is depending on various material (substrates) and process parameters. As shown by Rieutord et al. (1), and experimentally confirmed (2), for a given material and geometry, the speed is function of adhesion energy and fluid viscosity. For industrial applications, this means that investigating the bondwave speed by inline monitoring can be a way to monitor adhesion energy. Adhesion energy itself is a function of different parameters such as surface roughness, WET treatment or water presence (2,3).Inline IR monitoring can be also a practical solution for defect detection. Compared to post bond IR inspection, the live information allows for easier root cause analysis, e.g., particle defect, surface inhomogeneity or chuck effect. Inline early detection of defective bonds and process outliers enables bonded pairs to be reworked (separated and re-bonded) without any additional metrology steps such as post bonding IR inspection or Scanning Acoustic Microscopy (SAM). In case of fast bondwave, one has to monitor any unwanted effect such as edge voids or increased distortion (4).In an automated fusion bonding equipment, EVG®850LT, a bonding chamber has been equipped with an IR camera to record the bondwave propagation. The chamber has also connected different gas and vent lines and a humidifier to control the bonding atmosphere. The bond is initiated with a mobile pin equipped with a load cell, allowing to start the bondwave in a repeatable way at different locations (each bond must be initiated in a single point, but location might vary between center or edge proximity). As shown in figure 1 for a 300 mm Si-SiO2 bonded pair, spatial information can be extracted from the IR images, allowing for bondwave speed mapping (5). The equipment is also equipped with a plasma chamber for pre-processing. This allows to evaluate, using inline bondwave observation, various process conditions such as: plasma treatment, bond chamber gas type, pressure, humidity and bond pin location. Moreover, a metrology equipment was used for bonded pair shape measurement. This data is used to predict high resolution distortion maps to monitor the effect of bonding wave speed and bonding parameters.Different use cases of bondwave monitoring for process development will be presented, as well as the influence of different process parameters on bondwave propagation. A detailed analysis of the impact of the bond wave speed on bonded stack distortion will be presented. As shown in figure 1 (a) and (b), bonding wave velocity has no impact on high order distortion but will significantly increase the runout or scaling of the bonding pair.1. F. Rieutord, B. Bataillou, and H. Moriceau, Phys. Rev. Lett., 94, 236101 (2005).2. V. Larrey, G. Mauguen, F. Fournel, D. Radisson, F. Rieutord, C. Morales, C. Bridoux, and H. Moriceau, ECS Trans., 75, 145 (2016).3. D. Radisson, Phd thesis, Université Grenoble Alpes, (2014).4. M. Broekaart, A. Castex, K. Landry, R. Fontaniere, and C. Lagahe-Blanchard, ECS Trans., 50, 371 (2013).5. Fournel, F, B Rousset, V Larrey, C Morales, R Sachs, L Sudrie, and C Morvan, WaferBond’22 Proceeding, 2022. Figure 1

We present an approach for the heterogeneous integration of InP semiconductor optical amplifiers (SOAs) and lasers on an advanced silicon photonics (SiPh) platform by using micro-transfer-printing (μTP). After the introduction of the μTP concept, the focus of this paper shifts to the demonstration of two C-band III-V/Si photonic integrated circuits (PICs) that are important in data-communication networks: an optical switch and a high-speed optical transmitter. First, a C-band lossless and high-speed Si Mach-Zehnder interferometer (MZI) switch is demonstrated by co-integrating a set of InP SOAs with the Si MZI switch. The micro-transfer-printed SOAs provide 10 dB small-signal gain around 1560 nm with a 3 dB bandwidth of 30 nm. Secondly, an integrated transmitter combining an on-chip widely tunable laser and a doped-Si Mach-Zehnder modulator (MZM) is demonstrated. The laser has a continuous tuning range over 40 nm and the transmitter is capable of 40 Gbps non-return-to-zero (NRZ) back-to-back transmission at wavelengths ranging from 1539 to 1573 nm. These demonstrations pave the way for the realization of complex and fully integrated photonic systems-on-chip with integrated III-V-on-Si components, and this technique is transferable to other material films and devices that can be released from their native substrate.

We present an approach for the heterogeneous integration of InP semiconductor optical amplifiers (SOAs) and lasers on an advanced silicon photonics (SiPh) platform by using micro-transfer-printing (μTP). After the introduction of the μTP concept, the focus of this paper shifts to the demonstration of two C-band III-V/Si photonic integrated circuits (PICs) that are important in data-communication networks: an optical switch and a high-speed optical transmitter. First, a C-band lossless and high-speed Si Mach-Zehnder interferometer (MZI) switch is demonstrated by co-integrating a set of InP SOAs with the Si MZI switch. The micro-transfer-printed SOAs provide 10 dB small-signal gain around 1560 nm with a 3 dB bandwidth of 30 nm. Secondly, an integrated transmitter combining an on-chip widely tunable laser and a doped-Si Mach-Zehnder modulator (MZM) is demonstrated. The laser has a continuous tuning range over 40 nm and the transmitter is capable of 40 Gbps non-return-to-zero (NRZ) back-to-back transmission at wavelengths ranging from 1539 to 1573 nm. These demonstrations pave the way for the realization of complex and fully integrated photonic systems-on-chip with integrated III-V-on-Si components, and this technique is transferable to other material films and devices that can be released from their native substrate.

The concept of dual layer pattering as an alternative to POR in interconnect formation has been evaluated on maskless exposure technology. The novel dielectric materials negative tone PBO were used for the concept prove. The process optimization was conducted by varying the exposure and spin coating paraments. The lowest feature size accomplished was even <4 μm proving the two–step structures with FT of the first layer 50% of the dual layer FT. This new concept represents contribution to the improved CoO setup in the advanced packaging processes.

EVG's maskless exposure lithography enables 3D dual-image patterning of novel dielectrics replacing the cost consuming dual-damascene process in WLP. The pattern sizes <4 μm (bottom via) with layer thickness 8 μm were accomplished in this investigation. Unique features of LITHOSCALE® support variety of R&D designs, technology transfer to HVM and fast time-to-market of new designs in the growing semiconductor world.

As heterogeneous integration is increasingly adopted for semiconductor development and innovation, back-end lithography requirements are growing. More redistribution layers (RDLs) within the package are driving the need for finer RDL line/spacing (L/S) as well as smaller critical dimensions for micro-bumps and micro-pillars. In this work, digital lithography was used to demonstrate an efficient dual damascene process implementation with respect to RDL and interconnect scaling. Multi-level exposure was used to reduce 50 % of lithographic steps and to allow for simultaneous generation of RDL and via structures without alignment. The results showed well-defined patterns with lateral dimensions < 5 µm which enable a new manufacturing scheme for the dual-damascene process with significant reduction in complexity and process time.