Marvell (United States)

This paper introduces a unified algorithmic design flow for low-noise amplifiers (LNAs), spanning specifications to layout and integrating topology, architecture, circuit, and electromagnetic (EM) design in one framework. The algorithm supports designer input from classical to unconventional architectures, enhancing interpretability, debugging, and usability. We demonstrate two LNAs covering 24 to 150GHz with state-of-the-art performance, including novel architectures uncovered by the algorithm.

Transition metal dichalcogenides possess valley pseudospin, enabling coupling between photon spin and electron spin for classical and quantum information processing. However, rapid valley-dephasing processes have impeded the development of scalable, high-performance valleytronic devices operating at room temperature. Here we demonstrate that a chiral resonant metasurface can enable room-temperature valley-selective emission in MoSe2 monolayers independent of excitation polarization. This platform provides circular eigen-polarization states with a high quality factor (Q-factor) and strong chiral near-field enhancement. The fabricated Si chiral metasurfaces exhibit chiroptical resonances with Q-factors up to 450 at visible wavelengths. We reveal degrees of circular polarization (DOP) reaching a record high of 0.5 at room temperature. Our measurements show that the high DOP can be attributed to the significantly increased chiroptical local density of states, which enhances valley-specific radiative transition rates by a factor of ~13. Our work could facilitate the development of ultracompact chiral classical and quantum light sources.

We review EEPN effects across different spectral ranges. For coherent pluggables, 1/f noise -induced timing drift can be dominant. We show the bursty feature of resulting performance degradation. We discuss recent advancements in mitigation techniques. ©2025 The Author(s)

Chip Scale Packages (CSPs) have the advantage of smaller size and low package profile, lesser weight, relatively easier assembly process, lower overall manufacturing costs and improved electrical performance. However, the CSPs, particularly the ones built in the 2.5D and 3D System in Package (SiP) devices, have created significant challenges for failure analysis. In this paper, an overview of CSPs will be provided. Some failure analysis challenges, including fault isolation precision, non-destructive imaging, and sample preparation, will be discussed. Finally, solutions and best practices will be discussed, and two case studies will be shared on how to overcome some of the challenges.

We propose geometric shaping for IM-DD links dominated by relative intensity noise (RIN). For 400 Gbps links, our geometrically-shaped constellations result in error probability improvements that relaxes the RIN laser design by 3 dB.

A Clock Mesh is a structure commonly used in System-on-a-Chip (SoC) designs running at very high clock rates, typically beyond 2.0 GHz, to distribute a clock signal across a large region of a chip. The clock mesh typically is implemented using wires on two adjacent and orthogonal levels of metal in a chip, in which the wires are tied together at each point of intersection. Taps of the mesh are made as needed to service the clocking needs of logic below the mesh. A typical tap would normally service the clocking needs of an area that is in the order of 0.01 sq mm. Several taps are placed beneath the mesh to ensure coverage of the entire area of the block. In some SOC Designs, two or more synchronous clocks are needed to support logic which is placed below the clock mesh. Typically, the synchronous clocks are divided clocks. To meet the timing closure requirements of the logic, when logic of one synchronous clock drives logic associated with the other synchronous clock, it is necessary to provide precise alignment of the clocks, including precise alignment of coincident edges of the synchronous clocks. In this paper, we propose a method of supporting the requirement of multiple synchronous clocks with a single mesh and meeting the Design for Test needs of such designs.

Abstract To enable higher computing power in a single chip, there is demand for increasing die and substrate size for high performance applications in advanced nodes. Chip package interaction (CPI) performance is very critical for package reliability, specifically for advanced low-k 5nm, 3nm technology node chips including extreme low-k (ELK) and low-k (LK) dielectric materials. The material property coefficient of thermal expansion (CTE) mismatch between dielectric materials, copper, silicon can induce significant stresses, causing ELK-LK cracking or delamination and chip failure in electronic packages. For advanced semiconductor nodes like 5nm and 3nm, the Back End of Line (BEOL) structure mechanical strength is reduced due to the presence of porous material with low-dielectric constant which makes it more prone to thermal mechanical failures. On the other hand, use of stiff first level interconnect (copper pillars) together with large die, and package size causes an increased level of stress transfer from package to chip. For these reasons, die BEOL cracking or delamination due to Chip Package Interaction (CPI) is becoming more and more critical in advanced nodes and therefore necessary design optimizations should be done during initial package design phase to avoid any CPI related cracking or delamination failures in package. This study investigates in detail the impact of copper pillar design parameters such as copper pillar height, under bump metallization (UBM) diameter, copper pillar plating chemistry on die cracking or delamination within die BEOL structure. Novel fracture mechanics and stress-based with detail BEOL structure multi-level finite element analysis (FEA) simulation methodology based on the energy release rate (ERR) driving delamination using J-integral approach is developed to assess impact of various package parameters on cracking or delamination in die BEOL layer and used to assess die ELK cracking risk for advanced 5nm packages. Energy release rate (ERR) is the change in the elastic strain energy with respect to change in crack area. Critical ERR (ERRc) is material property also known as fracture toughness and it is used to estimate if the crack will propagate or not (crack will propagate if, ERR ≥ ERRc). This work is expected to provide design guidelines for package designers and help to optimize copper pillar structure for advanced 5nm packages.

We study the one-shot channel coding problem over classical and classical-quantum channels, where the underlying codes are constrained to be group codes. In the achievability part, we introduce a new distribution that incorporates the encoding homomorphism and the underlying channel law. Using a random coding argument, we characterize the performance in terms of hypothesis testing relative-entropies. In the converse part, we es-tablish bounds by leveraging a hypothesis testing-based approach. Further we apply the one-shot result to the asymptotic use case and establish the group capacities for both channels.

With die sizes reaching reticle limits and a persistent increase in the cost of advanced technology nodes, heterogeneous integration and chiplet-based designs are gaining exponential traction. Die-to-die interconnects are an integral part of chipletbased systems and are a subject of innovation and optimization for high-performance applications. Designing a die-to-die interface in an appropriate packaging architecture while adhering to industry standards is key to maximizing the benefits of a chiplet-based system. SerDes-based interconnects and parallel interfaces are commonly used for chiplet communication in standard and advanced packages respectively. Due to additional assembly and process steps, advanced packaging technologies are much costlier than standard 2D packaging technologies. This paper demonstrates a parallel interface in a standard 2D package, a costoptimized alternative, while providing moderate power and beachfront efficiency. The interface is designed in compliance with the standard package option of UCIe, which is an emerging industry standard for die-to-die interfaces. The package layout design was done to achieve a total wiring density of ~70 wires/mm. The design is observed to be close to voltage transfer function loss compliant at various distances up to 25 mm between the UCIe modules. The simulation data is validated by measurement data. This work utilizes analytical cost models to quantify the costbandwidth trade-off between chiplet designs in standard 2D and advanced 2.5D packaging. The impact of the technology node of the chips and the different 2.5D options available in the market on the cost analysis framework is also explored.

Purpose: In today's world, data is gathered without any particular objective in mind; every action taken by a computer, or a human being is documented, and the data is studied in the future, if it is considered important to do so. The data will be subjected to several steps for analysis by a variety of parties, which raises the issue of trust in this context. There is a risk that the organizations involved in the analytical stages may abuse the data, which might contain private or sensitive information. Consequently, data privacy considerations should be carefully considered at this time. Methodology/Findings: A definition of "data privacy" is the practice of limiting access to information according to how important it is. People are usually very comfortable giving out their names to strangers, but they'll wait to give out their mobile phone numbers until they're more familiar with the individual. In this era of digital technology, important personal information is often the target of individuals' efforts to protect their data. From a business's point of view, data privacy encompasses more than just employees' and consumers' private information. Data privacy issues are often believed to be a barrier to the widespread adoption of AI and ML-driven technology. The reason for this is that ML can only be trained and tested on very large data sets. Implications to Theory, Practice and Policy: Imagine a world where trust is impossible to establish; here is where Blockchain technology might be useful. Blockchain uses the data anonymously. In this study, we provide a solution that ensures data security by integrating Blockchain technology with machine learning (Alfandi et al., 2020).