Chip Scale Packaging and Its Failure Analysis Challenges (invited)

A low-cost, highly reliable UFI (UBM-free integration) wafer level chip scale packaging (WLCSP) for high performance, large die (>100 mm2) with fine solder ball pitch (350 µm) and high I/O (>800) has been developed. Reliability issues including solder cracking and high chip warpage are known to be the main challenges for extending the die size of conventional WLCSP to more than 5x5 mm2 with ball pitch smaller than 350 µm. In this paper, we present the novel WLCSP designed with a stress-mitigation structure which can significantly enhance the reliability of the package and enables die size extension. By controlling the maximum strain location and optimizing the materials using the stress-mitigation structure, the chip warpage and the stress between Si and PCB can be effectively reduced to enhance both component and board-level reliabilities of the package. The UFI WLCSP passed all component-level tests and exhibited board-level thermal cycle life that is 1.4 and 2.3 times longer than that of the conventional WLCSP in terms of the first failure and the Weibull distribution (t63), respectively. As a result, highly reliable packages with various die sizes, including 5.2x5.2, 7.2x7.2 and 10.3x10.3 mm2 and with both 400 and 350 µm ball pitches have been developed. The RDL within the package of UFI WLCSP can be utilized to form inductor structure which exhibits quality-factor nearly 50% higher than that of an on-chip inductor. Besides, in WLCSP process, die sawing typically causes delamination and cracking of packages which results in process failure in the WLCSP. The UFI unique structure consists of sidewall protection which is capable of preventing chipping and therefore effectively improves the process controls and the reliability margins. In addition, to fulfill the requirement of high I/O products and to enhance the design flexibility, we embedded multiple RDL in UFI WLCSP with die size of 10.3x10.3 mm2 and ball pitch of 350 µm, which provides a fan-in package solution with I/O >800. The large die UFI WLCSP has passed the component-level reliability tests of TCB1000, uHAST96 and HTS1000, and board-level reliability tests of TCG500 and drop tests.

Some of the critical issues of wafer level chip scale package (WLCSP) are discussed in this investigation. Emphasis is placed on the cost analysis of WLCSP through the important parameters such as wafer-level redistribution, wafer bumping, and wafer-level underfilling. Useful and simple equations in terms of these parameters are also provided. Furthermore, the effects of microvia build-up layers on the solder joint reliability of WLCSP on printed circuit boards (PCB) through creep responses such as deformation, hysteresis loops, and stress and strain are presented. Only solder-bumped WLCSPs with pad-redistribution are considered in this study.

A plastic chip-scale package (CSP) smaller than conventional packages has been developed and applied to ATM switching systems. The package uses a low-cost glass-epoxy substrate. As glass epoxy is widely used in the printed circuit boards (PCBs) of ATM switching systems, its use in the CSPs mounted on a PCB reduces the difference in thermal expansion between PCB and CSPs, thus lengthening CSP life. The power plane, ground plane, and thermal vias of the CSP are designed to offset the increased thermal resistance due to the CSP's smaller size. Simulation showed a thermal resistance for this CSP with copper layers and thermal vias of as much as 22% less than that of a CSP with no copper layers or thermal vias. A six-layer test board mounting four CSPs was used to simulate a sub-board for ATM switching systems. The thermal resistance of the two CSPs located downstream was about 10% higher than that of the two located upstream. Two CSPs were developed for two types of application-specific ICs: a bus interface controller (BIC) and a peripheral interface circuit (PIC). Both CSPs were 18 mm square with a 0.8 mm outer solder-ball pitch and 256 outer balls. These CSPs occupied areas about 87% and 68% smaller than those of a conventional pin grid array (PGA) and quad flat package (QFP) respectively. The junction temperature of both CSPs satisfied the thermal conditions. These high-performance CSPs are thus attractive for use in ATM switching systems.

In this work, a systematic study was performed in order to evaluate the influences of chip scale package (CSP) materials on the reliability of the soldered joints. The type of adhesive interconnecting the top and bottom layers of silicon was varied in this study. The materials alternatives evaluated comprise a hard epoxy material with high filler content, a rubber-like adhesive and an adhesive in medium state. These were combined with the substrate materials, FR4 and Al/sub 2/O/sub 3/, on which the CSPs are mounted. A unified viscoplastic constitutive model was applied to represent the temperature and time dependent deformation behaviour of the solder material. The stress/strain responses of CSP solder joints under thermal cycling conditions were evaluated using the finite element method. From the results, solder joint lifetimes were estimated with a crack propagation model. The results show that under thermal cycling conditions, the CSP solder joint lifetimes are lower when the CSP is fabricated with a highly filled adhesive compared to those with a rubber-like adhesive. Also, the solder joint reliability of CSPs mounted on FR4 substrates is inferior to those on Al/sub 2/O/sub 3/ substrates. This is due to the fact that the internal adhesive layer in a CSP also serves as the source of thermal expansion mismatch. Furthermore, a more flexible CSP design can reduce stresses in the soldered joints. Some discussions for material selection of epoxy adhesive in CSP are also presented. Consequently, a structural adhesive with a low elastic modulus and low CTE is more desirable than a harder material.

Wafer-Level Chip Scale Packages (WLCSPs) are becoming commonplace in the industry due to their small form factor. Applications include industrial and automotive which demand high reliability performance. Additionally, WLCSPs may be superior in some implementations to other package options for RF performance in the mmWave spectrum, which is desired for automotive radar application. But board level reliability can be a challenge for some WLCSP package due to CTE mismatch between Si and PCB. Variety of factors including PCB materials, sphere alloys, and board level underfills can influence the board level reliability of WLCSP packages. In this study the industry’s first auto grade 1 capable large WLCSP package. (~ 72 mm 2 body size, 18×15 BGA array, 0.5 mm pitch) is presented. Board level underfill application was utilized to achieve automotive grade board level reliability. Underfills are typically selected based on thermomechanical properties of unaged materials. An understanding of the evolution of underfill material properties under thermal aging is important for selecting a stable material capable of meeting the reliability requirements. This study evaluates board level underfills and edge bond materials in the form of stand-alone samples and applied to a large daisy-chain WLCSP. The underfilled daisy-chain WLCSPs and the stand-alone samples are placed in a -40/125C air cycling chamber (1 cycle/hour). Glass transition temperature (Tg), elastic modulus (E), and coefficient of thermal expansion (CTE) are measured using Dynamic Mechanical Analysis (DMA) and Thermomechanical Analysis (TMA) on the stand-alone samples at various intervals to monitor the evolution of material properties. Simultaneously, the underfilled daisy chain WLCSPs are monitored electrically using an event detector. The combination of material property measurements and cycles to electrical failure can be used to correlate underfill material properties and WLCSP board-level reliability. The results of this study can provide material property guidance for underfill selection.

Ball Grid Array (BGA) packages with 1.27 mm pitch arrays are now being extended to fine pitch BGAs, or Chip Scale Packages (CSP) with ball diameters of 0.3 mm and array pitches as small as 0.5 mm. The current work analyzes the impact of integrating such packages into a high volume SMT assembly line and examines the impact of process and board variables on the reliability of the total assembly. The CSP chosen for the current study was a 0.75 mm pitch CSP scheduled to replace the 0.5 mm lead pitch Thin Small Outline Package (TSOP) currently used in high volume, small form factor, flash memory products. The CSP dimensions of approximately 5.6 mm by 7.4 mm represents an 80% reduction in package area compared to the traditional TSOP, with a footprint of 12 mm by 20 mm. The study examines the effect of solder paste printing parameters, flux-only assembly, and printed circuit board surface finishes such as immersion gold and solder-leveling. Solder paste volume measurements were made on over 2800 individual CSP pads during the builds using an in-line, automated laser scanning profilometer. Reliability test vehicles were assembled using CSPs, TSOPs and other surface mount components, prior to performing accelerated thermal cycling tests from 0/spl deg/C to 100/spl deg/C, and 40/spl deg/C to 85/spl deg/C. CSP placements were performed using optimized high speed chip placers to place CSPs at rates of up to 5 parts per second. Interim reliability test results after four months of testing are presented with a discussion of TSOP versus MicroBGA package construction.

This paper documents a chip scale package (CSP) cost analysis using SEMATECH's Cost/Resource Model (CRM). The intent of the analysis was to compare costs between CSPs and conventional package technologies such as the thin small outline package (TSOP) and ball grid array (BGA) to determine whether CSP is a viable packaging technology. The analysis includes costs of both package and board assembly components in a high volume, mature production factory. Four representative CSP types (custom lead frame, flex circuit interposer, rigid substrate interposer, and wafer level assembly) and three traditional surface mount package configurations (plastic ball grid array [PBGA], ceramic ball grid array [CBGA], and thin small outline package [TSOP]) were selected to benchmark. By selecting CSPs across many applications and I/O ranges, the goal was to study a cross section of CSPs that were in or near production. Analysis results indicated that CSPs with a low I/O count are cost-competitive with conventional surface mount packages and can be used with the existing printed circuit board (PCB) infrastructure. However, CSPs with a high I/O count are not currently supported by conventional PCB technology and are not cost-competitive with conventional surface mount package technology.

Along with the trends of the product minimization, wafer level chip scale package (WLCSP) has become a new solution to advanced packaging. Formation of micro-vias with desired patterns is a critical process step. Currently micro-vias are achieved through photolithographic technology, which is lengthy and time-consuming. In order to improve the productivity and reduce the cost of the via formation process, it is critical to develop a simpler and more cost-effective drilling technology. The successful application of laser drilling in printed circuit boards promted us to apply the technology in drilling microvias of WLCSPs. The critical new challenges of the laser drilling of WLCSPs are the requirements of forming straight-walled vias on a thin copper layer (less than 1 µm). The laser-drilled vias need to be free of residues for subsequent electroplating of copper bumps. In this paper, we report our experimental results using a Q-switched CO2 laser.Along with the trends of the product minimization, wafer level chip scale package (WLCSP) has become a new solution to advanced packaging. Formation of micro-vias with desired patterns is a critical process step. Currently micro-vias are achieved through photolithographic technology, which is lengthy and time-consuming. In order to improve the productivity and reduce the cost of the via formation process, it is critical to develop a simpler and more cost-effective drilling technology. The successful application of laser drilling in printed circuit boards promted us to apply the technology in drilling microvias of WLCSPs. The critical new challenges of the laser drilling of WLCSPs are the requirements of forming straight-walled vias on a thin copper layer (less than 1 µm). The laser-drilled vias need to be free of residues for subsequent electroplating of copper bumps. In this paper, we report our experimental results using a Q-switched CO2 laser.

Reliability of flip chip CSP (Chip Scale Package) was investigated. The underfill resin for CSP has high saturation content of moisture absorption, compared to a conventional mold resin. The IR reflow test showed no delamination at the underfill interfaces and no package cracking in a flip chip CSP with a ceramic substrate and voidless underfill under the JEDEC LEVEL 1 and 2 conditions. However, it was found out that delamination and package cracking occurred in the IR reflow test under the JEDEC LEVEL 1 when the flip chip CSP has voids in the underfill. The underfill reliability results by IR reflow test confirmed superior reliability of the flip chip CSP with a ceramic substrate and void controlled underfill.

Chip scale packages have seen a growth of over two times in the last two years and are expected to have more demands in the booming telecommunications market. This rapid growth of chip scale packages combined with green packaging solutions has made the implementation of lead free solders for chip scale package applications inevitable. But the effect of various lead free solders on the wetting behavior and their mechanical strength and the under bump metallization (UBM) integrity are also important to achieve a reliable chip scale package. This paper presents a methodology of implementation of lead free solder in the first and second level interconnects as a replacement for eutectic tin lead (SnPb) solder in chip scale packages developed for wireless applications. No clean solder paste made with alloys Sn/Ag (Supplier a), Sn/Ag/Cu (Supplier B), CASTIN (Supplier C) and SnBi (Supplier D) from various vendors have been evaluated for the implementation. The process evaluation conducted in this research study investigated the following aspects i) occurrence of voids ii) Effect of lead free solder on the UBM metallization, iii) wetting behavior of the lead (Pb) free solders, iv) thermal aging and shear strength of the, lead free solders in first and second level process and v) accelerated thermal cycle experiments on assembled lead free solder samples.

With the dynamic progress in electronic packaging, possessing a small chip size the Wafer Level Chip Scale Package (WLCSP) is one of the most cost-effective and space-efficient package in the industry. Having dominated the field over a decade, WLCSP still faces a huge issue in developmental phase in form of Solder Joint Reliability as the solder undergoes progressive inelastic deformations over time under constant cyclic Thermo-Mechanical loading. This time dependent deformation is called creep. Constitutive Creep Models have been constantly deployed in finite element modelling in order to eradicate the costly and time consuming experiments such as Accelerated Thermal Cyclic Testing. Various creep models have been proposed so far and Anand Model is considered to be the most prominent one. Also many researchers are concerned about altercations over the negligence of the primary creep in Anand model and the typical prediction of its nine parameters. In this research work, a new hyperbolic Sine form creep model based on the steady state behavior of Anand Model called Modified Anand Model with lesser parameters is developed to have a better characterization of the creep behavior in solders. Assuming the saturated stress condition of Anand Model leads to the derivation of the four parameters meant for the new model. Thus the stress-strain relationship formation of the new model resembles Garofalo-Hyperbolic Sine Model illustrating the steady state creep behavior of the solder. In order to have a better realization of the Hyperbolic Sine Model, simulations are conducted using both the Anand and Hyperbolic Sine Model creep models over a WLCSP under JEDEC-G condition. From the simulation results, it is observed that the resultant strain energy density of the Hyperbolic Sine model has a better agreement than that of Anand Model to the experiment results. The investigation for the cause of variation points out significant findings. It is understood that the hardening effect in solder is due to the stress induced by high temperature creep in Anand Model. Also the presence of a short lived primary creep in Anand model is noticed which occurs as a setback in achieving the steady state creep. By modifying the parameters of the Anand model to neglect the hardening effect, the ability of Hyperbolic Sine Model to predict the lifetime is comparatively better than the Anand model within 10% of the experimental data. Thus we conclude that the uncertainty in determination of the Anand model parameters has brought up the new model to estimate the failure of solders joints and an elegance scheme to compute with precise outcomes.

Wafer Level Chip Scale Package (WLCSP) technologies are being used more often in electronic components due to their smaller size and lower cost, and are being applied to larger die and ball matrix sizes. Originally implemented mainly in mobile devices (i.e., smartphones), WLCSP components are now frequently used in new product categories that have more stringent use conditions than the mobile space. The harsher use conditions raise a concern of solder joint reliability, especially in temperature cycling due to the difference in the coefficient of thermal expansion between the silicon die and the laminate motherboard. While cycle life can be extended by using underfill, underfilling makes the surface mount assembly process more complex and costly, increases cycle time and inhibits rework. To solve the challenge of extending cyclic life without underfill, new WLCSP structures and materials have been proposed. This paper describes the investigation of some of these innovative solutions through motherboard assembly and board level reliability testing. The package variables consisted of two WLCSP structures utilizing ball support mechanisms and a Bismuth (Bi) bearing solder ball that is expected to increase fatigue life. Packages were produced separately with each variable, along with legs that included both new packages and new alloy. The finished assemblies, along with a control leg of standard structure/solder, were subjected to drop testing and temperature cycling. Solder joint integrity was monitored in-situ to accurately identify duration to failure for Weibull analysis. The results clearly show that this new generation of WLCSP structures can offer dramatically improved fatigue life without a significant sacrifice in drop reliability. This benefit should allow the use of WLCSPs in more challenging environments, as well as providing designers the option of using larger package sizes in existing mobile designs.

The solder‐joint reliability of solder‐bumped wafer level chip scale package (WLCSP) on microvia build‐up printed circuit board (PCB) subjected to thermal cycling conditions is investigated in this study. The 62Sn36Pb2Ag solder joints are assumed to be: an elastic material; an elastic‐plastic material; and a creep material which obey the Garofalo‐Arrhenius steady‐state creep constitutive law. The stress and strain in the corner solder joint of the WLCSP assembly are presented and compared for these three material models. Also, the results presented herein will be compared with that from creep analysis of the WLCSP on PCB without microvia build‐up layer.

To solve the mystery of early thermal cycling failures on a relatively small size (1.6 mm × 2.4 mm) wafer level chip scale package (WLCSP) with bump on re-passivation (BOR) structure, details of bump geometry parameters are looked into. While the under bump metal layer stack is first confirmed within specifications, UBM offset from center point is found greater than typical on the failed units. To fully understand the impact of this bump parameter shift that is defined by lithographic process, additional geometric configurations of the bump structure and materials, as well as bump parameter deviations are studied on the stress in solder, UBM and on chip SiN passivations. The study takes into consideration the thickness/size of UBM, aluminum metal pad, SiN passivation layer and PI re-passivation layer. UBM materials, such as nickel vs copper, are also included in the study. Board-level thermal cycling test (TMCL) is conducted on a WLCSP with 8×8 bump array at 0.4mm pitch. Simulation reveals that size ratio and bump offset indeed change the stress level in the critical passivation layer, and the results well explain the early failures recorded in a device qualification reliability test and follow up experimental verifications. Conclusion of this work should be applied when defining design rules for robust reliability performance and manufacturability of this traditional WLCSP bumping technology.

The demand on reliable Wafer level chip scale packages (WLCSP) are getting higher due to the need of small form factor and cost. As demonstrated in earlier publications the degradation and deformation mechanism show microstructure evolution associated with the thermal cycling induced damage accumulation. The mechanism, leading to crack initiation and propagation during thermal cycling by sub-grain boundary development can be observed as a general damage accumulation mechanism in various solder joints. The correlation between crack propagation and localized recrystallization are compared in a series of cross section analyses on thermal cycled WLCSP components with normal and elevated temperature thermal cycling conditions. Damage accumulated solder joint locations are identified and an attempt of using edge-bond materials to strengthen the localized solder joints demonstrate that the Tg and CTE needs adjustment to have the thermal cycling performance enhancement. Edge-bond material applied components show either a shift of damage accumulation to a more localized region, thus potentially accelerated the degradation, or mitigate the distribution resulting in an enhancement of thermal cycling based on their Tg and CTE properties. The edge-bond applied WLCSPs were thermally cycled from 0oC to 100oC with 10min. dwell time, and to simulate the function temperature environment, components were also tested at elevated temperature cycles for comparison. Using an analysis on localized distribution of recrystallized areas inside the solder joint provide more information on the localized microstructure evolution during thermal cycling. The results show that the crack propagation distribution and recrystallization region correlation can explain the enhancement and potential degradation mechanisms and support the damage accumulation history in a more efficient way.