Synopsys (Germany)

Patterning with high-NA EUV lithography has become an inevitable option as the semiconductor industry seeks singlepatterning solutions. However, High-NA EUV modeling presents new challenges due to the anamorphic nature of scanner optics. Lithographers must consider not only the data at the center of the field, but also from the stitching regions where black border and double exposure effects can be significant. Therefore, an accurate topographic mask model is required to account for mask background reflectivity in both areas, with various EUV absorbers. Furthermore, novel metal-oxide photoresist (MOR) creates additional challenges in metrology, imaging, and modeling, due to the thin resist film and postdevelopment resist profiles. Additionally, long-range flare effects beyond the EUV optical influence range, such as optical and chemical flare, must be considered. Thus, a well-calibrated rigorous model reference is essential for validating the quality of the wafer data and to serve as a good starting template for compact modeling. In this paper, we show the importance of advanced metrology and modeling through experimental data. A novel modeling flow of advanced offline metrology, state-of-the-art modeling and validation technology is demonstrated. More specifically, we show that offline CD extraction can generate a modeling input dataset with precise CD valuesfrom accurate design-wafer image registration, especially for 2D patterns. By combining the techniques described, a comprehensive modeling flow of High-NA EUV OPC modeling is demonstrated. The results show that this approach meets the precision requirements for OPC applications in the advanced nodes.

Accurate prediction of patterns susceptible to rare stochastic failure has been a key goal for EUV lithography modeling since the initial use of EUV lithography in production processes. This goal has been difficult to achieve for several reasons, including quantification of stochastic effects in photoresist chemistry interactions, mask variation contributions in all three-dimensions, and measurement uncertainty. Another difficulty has been the extremely large number of experiments needed to calibrate and validate stochastic models for high sigma (very rare) pattern defectivity rate, both for wafer experiments and for rigorous Monte Carlo statistical simulations. In this paper, we investigate and show results from algorithmic enhancements to generate significantly faster rigorous statistical simulations which can enable accurate rigorous high sigma pattern defect simulation in a reasonable time. We then use these enhancements to build and validate accurate full-chip capable through-sigma defect printability compact models.

New applications such as autonomous driving, cyber-physical systems, or remote surgeries demand integrated circuits (ICs) with an ever-lower tolerance for failure. Typical IC design focuses on the targets of functionality and power, performance, and area. An emerging topic in IC design is trustworthiness. It attempts to unify the various interdependent functional and non-functional aspects, such as correct functionality, reliability, security, and functional safety. Existing methodologies and standards focus on evaluating trustworthiness issues (TIs), i.e., causes of faults, and their effects on only one particular attribute. Instead, TIs should be evaluated on their effect on trustworthiness as a whole, which demands a holistic approach. In this paper, we make two main contributions. The first contribution is a framework with a set of unified evaluation criteria that can be applied across all trustworthiness attributes, and a metric, called the Residual Risk Value (RRV). The latter can be used to assess the residual risk of a TI, where a low RRV indicates low risk remaining, and vice versa. RRV considers the impact and likelihood, and the potential for risk reduction enabled by implementing countermeasures. The second contribution is a questionnaire-based measure that ranks TIs according to the priority of addressing them. The results highlight that TIs that emerge during the early stages of IC development should be treated with greater priority. Further, there is a tendency to prioritize security-related TIs as a greater risk to trustworthy ICs. Meanwhile, TIs affecting well-established aspects of IC design and verification are given a lower priority.

High numerical-aperture (NA) extreme ultraviolet lithography (EUVL) system has been highly desired [1-3] and is now under construction at imec-ASML high-NA laboratory in Veldhoven. However, there are still many challenges to realize high-volume manufacturing (HVM) by high-NA EUVL; Line edge roughness (LER) mitigation is one of the key elements. In our previous research, we studied how normalized image log slope (NILS) and resist film thickness (FT) affect resist LER by exposure at NA 0.33 on NXE:3400 and S-Litho EUV [4] . However, mask absorber/tone, exposure dose and postexposure bake (PEB) temperature were not focused on for decreasing LER. They have the potential to mitigate resist roughness as illumination and resist thickness also have. Unbiased LER (uLER) values of metal oxide resists (MOR) were experimentally measured on half pitch 14 nm line and space (L/S) under several mask absorber/tonality, dose and PEB temperature. Per mask absorber/tone the NILS was varied by using different illumination shapes. Low-n masks exhibited higher NILS for the same illumination shape, which resulted in lower resist LER on wafer. It was also found that mask tone can contribute to LER mitigation. According to detailed investigations about mask roughness, mask error enhancement factor (MEEF) and flare by CD-SEM measurements and S-Litho EUV, the most likely reason for LER difference is flare increase given by mask tone change. From dose and PEB temperature variation study, dose was apparently more dominant to resist roughness than PEB temperature.

The lithography industry has historically striven to improve resolution by reducing wavelength and increasing the lens’ numerical aperture (NA). The introduction of 0.33 NA extreme ultraviolet (EUV) lithography into high-volume manufacturing (HVM) represents the largest jump in resolution ever achieved by the industry. However, even this resolution is not sufficient for the patterns required for beyond the 2 nm logic technology node. This is due to low contrast and the diffraction limit of current EUVL scanners for the mask patterns required for these nodes. Instead, the resolution must be improved by increasing the NA. This will also increase the contrast of patterns which had insufficient contrast at 0.33 NA, which will in turn improve LCDU and defectivity. This change is not without its challenges though. Increasing the NA from 0.33 to 0.55 will cause a significant reduction in depth of focus. In addition, stronger mask 3D effects can cause pattern dependent shifts in best focus. As a result, the common overlapping process window of several critical patterns can become strongly diminished. The use of anamorphic optics will require two separate half-field exposures to obtain the equivalent of a single full-field exposure on current EUV and DUV scanners. For some chip sizes, this will require stitching two half-fields together to pattern the full chip area. In previous technology nodes, the process window could be improved using SMO and SRAFs. In addition, over the last five years, the industry has put significant effort into studying alternative absorbing materials. These materials can significantly reduce the mask 3D effects by reducing the thickness of the absorber. The use of alternative absorbers alone will not be sufficient for improving the overlapping process window. Instead, several techniques must be simultaneously utilized in order to ensure sufficient overall process window. Optimization of overlapping process windows is critical for successful insertion of high-NA EUVL into HVM. In this paper we analyze how the process window of critical patterns can be optimized by using different optimizations. We will show for realistic mask designs how process window can be improved in different process steps. Double exposure from half-field stitching will also be included in the process evaluation. We use both rigorous and compact modeling in a complimentary fashion for overall process optimization analysis. All techniques presented in this paper accurately model the anamorphic, centrally obscured optics of the upcoming next-generation high-NA scanners.

Extreme ultra-violet lithography lithography resolves features below 11 nm. However, photonic and atomic variations at these photon energies and dimensions lead to less than 1:109 potential stochastic defects causing device failures in stable manufacturing processes. This study investigates a methodology intended to identify root causes of stochastic defects with potential mitigation paths. Simulation techniques using pseudo random numbers are used to identify failing photonic and chemical event or distribution combinations. Failing combinations occurring in many photon-chemical configurations are thought to have potential mitigation methodologies. Photonic effects demonstrated significant impacts on stochastic defect formation with approximately 73% of the photon seeds resulting in a failure in at least 60% of the trials. The material results were mixed with large failure quantities that demonstrated low impacts. The photonic shot noise based failures were dominating in this study and these failures will not be mitigated by material enhancement alone.

As minimum feature size shrinks to a metal pitch of 21 nm, the current extreme ultra violet (EUV) lithographic tool with a numeric aperture (NA) of 0.33 will face resolution limit for some critical layers. High NA (0.55) EUV with anamorphic optics or EUV double patterning (DP) at 0.33 NA are being considered for the next generation of lithographic technology. Both the high NA EUV system and EUV DP will enhance resolution relative to current EUV single patterning (SP). Nevertheless, in order to be able to compare EUV DP and High NA EUV processes, important lithographic factors including image contrast, mask three dimension (M3D) effects, process variation band, stochastic effects and local critical dimension uniformity need to be investigated to understand their contributions to process variations. This study was carried out using rigorous lithographic model simulations in Sentaurus Lithography, where strong M3D effects in EUVL are computed physically. We have simulated patterns with both isomorphic and anamorphic optical proximity corrections (OPC) using the rigorous model. The study focuses on 3nm node Via layer designs. These vias need to connect to metal features which have pitches of 21 nm. Simulation results using 0.33 NA SP, 0.33 NA DP, and 0.55 NA anamorphic SP are presented. The benefit of using an alternative mask absorber and a thinner resist as well as the impact of stochastic effects have also been explored. Although a 0.55 NA EUV is expected to produce a superior image to 0.33 NA EUV and to have less impact from overlay errors and stochastic effects, an analysis of process margins of 0.33 NA EUV SD and DP versus 0.55 NA anamorphic systems helps to better understand the benefits, challenges and optimal insertion point for introducing High-NA EUV.

Virtual platforms have become essential tools in the design process of modern embedded systems. Their accessibility and early availability make them ideal tools for design space exploration and debugging of target specific software. However, due to increasing platform complexity and the need to simulate more and more processors simultaneously, performance of virtual platforms degrades rapidly.