2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures

We proposed a novel pre-bond functional test architecture for core-level partitioned 3D SoCs. In this test architecture, a new test access mechanism is built by probing functional Through Silicon Vias (TSVs) and by linking functional TSVs to all pins of IP cores under test. In order to reduce the Design-for-Test (DfT) cost, we propose a novel scheme to share the functional TSVs among pins of IP cores and reuse wires which connect pins to the same functional TSVs. Experimental results based on the MCNC benchmarks circuits demonstrate the feasibility and effectiveness of the DfT optimization methods.

Advancement of VLSI technology helps semiconductor industry to manufacture Through-silicon-via (TSV) based 3D stacked ICs (SICs). During 3D assembly, multiple partial stack tests are necessary. In this paper, we address test architecture optimization for 3D stacked ICs implemented with hard dies. We consider two different test sets and derive optimal solutions to minimize over all test time when complete stack and multiple partial stacks, need to be tested. Results are performed for two handcrafted 3D SICs comprising of various SoCs from ITC'02 SoC test benchmarks. In this work we consider the test architecture optimization for 3D SIC where the die level test architecture is fixed and each die consists of one SoC. We show that decrease in total test length with the increasing number of test pins is more than increase in the number of test TSVs. Furthermore, we also present test schedules and corresponding test lengths for every multiple insertions.

<p>Information technology-to-internet of things may have succeeded because of fast silicon chip capability expansion. Moore's law, which reduces device size, boosted integrated circuit (IC) performance. Delay rises with highdensity connection parasitic capacitance. Interconnect delays have surpassed transistor delays and slowed progress. An alternative is required now to reduce connection latency. The third dimension is used in popular 3D IC technology IC technology requires through silicon via (TSV) for signal integrity and heat mitigation. Noise coupling hinders electrical communication between signal-carrying TSVs (aggressive TSVs) and ground TSVs (victim TSVs), a 3D IC bottleneck. TSVs must be dielectrically insulated from Si substrates to avoid electrical signal interference. Additionally, first-order modelling will confirm the suggestions. This article proposes using the nanosheet field effect transistor (NSFET) to overcome 3D IC noise coupling and complementary metal oxide semiconductor (CMOS) technology nodes. After discussing the electronic industry and sub nm, several basic metrics and criteria for developing electronic components are presented. The first technique uses Perylene-N's exceptional noise-cancelling characteristics. Second technique uses electrical TSV (ETSV), thermal TSV (TTSV), and heat source models to measure noise coupling on numerous ICs. The third proposes many noise-reducing materials. The suggested structures outperform traditional approaches.</p>

Through silicon via (TSV) based 3D integrated circuits have inspired a novel design paradigm which explores the vertical dimension, in order to alleviate the performance and power limitations associated with long interconnects in 2D circuits. TSVs enable vertical interconnects across stacked and thinned dies in 3D-IC designs, resulting in reduced wirelength, footprint, faster speed, improved bandwidth, and lesser routing congestion. However, the usage of TSVs itself gives rise to many critical design challenges towards the minimization of chip delay and power consumption. Therefore, realization of the benefits of 3D ICs necessitates an early and realistic prediction of circuit performance during the early layout design stage. The goal of this thesis is to meet the design challenges of 3D ICs by providing new capabilities to the existing floorplanning framework [87]. The additional capabilities included in the existing floorplanning tool is the co-placement of TSV islands with circuit blocks and performing non-deterministic assignment of signals to TSVs. We also replace the wirelength and number of TSVs in the floorplanning cost function with the total delay in the nets. The delay-aware cost function accounts for RC delay impact of TSVs on the delay of individual signal connection, and obviates the efforts required to balance the weight contributions of wirelength and TSVs in the wirelength-aware floorplanning. Our floorplanning tool results in 5% shorter wirelength and 21% lesser TSVs compared to recent approaches. The delay in the cost function improves total delay in the interconnects by 10% - 12% compared to wirelength-aware cost function. The influence of large coupling capacitance between TSVs on the delay, power and coupling noise in 3D interconnects also offers serious challenges to the performance of 3D-IC. Due to the degree of design complexity introduced by TSVs in 3D ICs, the importance of early stage evaluation and optimization of delay, power and signal integrity of 3D circuits cannot be ignored. The unique contribution of this work is to develop methods for accurate analysis of timing, power and coupling noise across multiple stacked device layers during the floorplanning stage. Incorporating the impact of TSV and the stacking of multiple device layers within floorplanning framework will help to achieve 3D layouts with superior performance. Therefore, we proposed an efficient TSV coupling noise model to evaluate the coupling noise in the 3D interconnects during floorplanning. The total coupling noise in 3D interconnects is included in the cost function to optimize positions of TSVs and

Convergence and miniaturization of consumer electronic products such as cameras, phones, etc. has been driven by enhanced performance and reduced microelectronics size. For past few decades Moore’s law has been driving the microelectronics industry to achieve high performance with small form-factors at a reasonable cost. While the continued miniaturization of the transistors has resulted in unparalleled growth of the electronics industry, further performance increment via size scaling could be cost-ineffective and difficult to manufacture. To satisfy the current/future integrated Circuit (IC) package requirements, vertical integration of chips holds the key, i.e., 3-D packaging. Chip-stacking (3-D) is emerging as a powerful technology to reduce package footprint, decrease interconnection power, higher frequencies, and provide efficient integration of heterogeneous devices. It allows further reduction in the form factor of current systems and eases the interconnect performance limitation since the components are integrated on top of each other instead of side-by-side, resulting in shorter interconnect lengths. Due to high package density and chip-stacking on top of each other, heat dissipation from the stacked chips becomes a concern. To overcome these thermal challenges and provide shorter/faster inter-chip electrical connection, Through Silicon Via (TSV) technology is being implemented in 3-D ICs. TSVs allow 3-D chips to be interconnected directly and provide high speed signal propagation. TSVs provide inter-chip heat/current path but the current flowing through the TSVs results in localized heat generation (Joule Heating) within the silicon, which could be detrimental to the overall performance of the system. In this paper, the effect of Joule heating on the device performance measured by trans-conductance, electron mobility (e− mobility), and channel thermal noise is analyzed. Thinned (100 μm) chips with a uniform power map and evenly distributed TSVs are analyzed in this work. Thermal distribution in the package is studied for different TSV currents including a base-line case of no-current (thermal TSV only) and the junction temperature is determined for each case. The response from the thermal analysis is correlated to the device performance through existing relations. Results indicate that joule heating has a significant effect on the thermal response of the 3D IC and subsequently proves to be detrimental to the chip performance. An understanding of the electrical performance dependence on TSV joule heating is developed through this work.

Through silicon vias (TSV) are an enabler for high performance Three Dimensional Integrated Circiuts (3DIC). TSVs are used for signal, power and ground lines in 3DICs. TSVs used to carry signals can induce noise in nearby circuitry and in those instances shielding is required. Traditional shielding is composed of guard rings surrounding the signal TSVs or if the signal is differential in nature, a careful arrangement of TSVs carrying the differential signals can aid in noise reduction. In the guard ring scenario, the guard rings are typically tied to ground. This paper proposes a technique for energy scavenging utilizing the guard rings for shielding TSVs. Energy absorbed by the guard rings can be stored for later use by the system. This paper examines the feasibility of configuring the guard rings to charge a decoupling capacitor instead of shunting energy to ground. It is shown that the decoupling capacitor can be charged using this method and that under certain conditions, the overall power of the system can be reduced by 4% to 15%

3D IC technologies are now approaching the innovation and business activities of semiconductor industries. 3D IC can be heterogeneous from different chip, interposer or substrate to integrate into a single package by using through silicon via (TSV) technique. With increasing functionality and performance at minimum cost and power dissipation, wide I/O memory VLSI technologies are being aggressively scaled to meet this demand. Stack memory chips using TSV technique will lead to increase a significant manufacturing challenge for semiconductor industries. TSV formation and interconnected reliability on the intermetallic compound (IMC) between the metal-metal bounded micro-bumps are crucial for 3D IC technologies. As the number and power of IC increases, lots of heat will be generated and, in turn raises the junction temperature. This will greatly deteriorate the performance of IC. Heat dissipation for 3D IC, when the power density exceeds 100W/cm2, is an important design concern before marketing. In this paper, high density TSV formed by an ultrafast pico-second laser to evaluate the behavior between manufacturing process and silicon material is presented. In addition, thermal management using finite element analysis to predict the reliability of TSV model is demonstrated.

Through-silicon via (TSV) based 3D integrated circuit (IC) testing is promising area to the researchers in modern day semiconductor industry. The manufacturing of 3D ICs may produce TSV defects which reduce yield. Recent work has proposed grouping of functional and redundant TSVs such that the faulty functional TSVs are supported by redundant TSVs and multiplexers (MUXs) are used to implement that group. This paper proposes grouping of functional and redundant TSVs such that a functional TSV is supported by redundant TSVs of other groups. We have presented an algorithm that finds the best grouping of functional and redundant TSVs such that maximum recovery of functional TSVs can be achieved with a given number of MUXs.

Through silicon via (TSV) based 3-dimensional integrated circuit (3D IC) has become the key solution to satisfy continuously increasing demands for small form factor, wide bandwidth, high performance, and low power consumption on electronic devices. However, there still remain several challenges to be solved; one of the most significant issues in 3D IC is TSV to active circuit noise coupling. In this paper, we analyzed the noise coupling between TSV and LC-VCO, which is an important component in RF communication system. When TSV is located near LC-VCO, the noise can easily travel through silicon substrate to the body of MOSFETs in LC-VCO. The noise coupling mechanisms of TSV to PMOS and NMOS are analyzed by voltage transfer functions in frequency-domain obtained by 3D electromagnetic solver simulation. The voltage transfer function between TSV and MOS is analyzed under variations of several physical parameters to clarify the tendencies of noise coupling. In addition, the noise coupling effect on PMOS and NMOS in LCVCO are investigated and compared in terms of sensitivity, such as phase noise.

Through silicon via (TSV) is one of the key components of the emerging 3D ICs. However, increasing number of TSVs in smaller silicon area leads to some severe negative impacts on the performance of the 3D IC. Growing signal integrity issues in TSVs is one of the major challenges of 3D integration. In this paper, different materials for the cores of the vias and the interposers are investigated to find the best possible combination that can reduce crosstalk and other losses like return loss and insertion loss in the TSVs. We have explored glass and silicon as interposer materials. The simulation results indicate that glass is the best option as interposer material although silicon interposer has some distinct advantages. For via cores three materials — copper (Cu), tungsten (W) and Cu-W bimetal are considered. From the analysis it can concluded that W would be better for high frequency applications due to lower transmission coefficient. Cu offers higher conductivity, but it has larger thermal expansion coefficient mismatch with silicon. The performance of Cu-W bimetal via would be in between Cu and W. However, W has a thermal expansion coefficient close to silicon. Therefore, bimetal Cu-W based TSV with W as the outer layer would be a suitable option for high frequency 3D IC. Here, we performed the analysis in terms of return loss, transmission coefficient and crosstalk in the vias.

In this research, a BIST (built in self test) architecture for testing crosstalk effects in highly dense Through Silicon Via (TSV) placed in structured array form, in 3DICs (Three Dimensional integrated circuits), designed and simulated using the Xilinx ISE tool and the VHDL language. A novel methodology is proposed, and simulated, to observe the test responses of the victim TSVs in the chosen group simultaneously. Boundary-scan cell structures are modified, created for the purpose of operating in different modes such as shift, update and capture in either conventional serial shift mode as well as in proposed parallel broadcasting mode. Output Response Analyzers (ORA), or signature analyzers that have been simulation-verified. In this study, we suggested a novel encoder-based signature generator to locate faulty TSVs in the parallel-observed TSVs. This paper discusses the whole BIST architecture, the BIST controller built on an algorithmic state machine, the design of TPG (Test Pattern Generator), and the faulty TSV signature generator. Comparing the BIST architecture, to serial shift based interconnect tests done by IEEE 1149.1 (JTAG) such as EXTEST and IEEE 1838 standards, the test’s time complexity of BIST is relatively very low. The entire TSV array test is completed in just 32 clock cycles. The design is adaptable and can be used to broadcast test patterns to a group or to transmit test patterns serially using IEEE 1838 or 1149.1.

Design of through-Silicon-Via (TSV) based 3D IC is became feasible recently. Testing of TSVs is an important issue in this respect. It is a challenge to test the TSVs before the bonding of different layers so that the manufacturing defects of TSV can be identified properly. In this paper, we are trying to test the TSVs before bonding. Here we have proposed a heuristic algorithm to locate the faulty TSVs uniquely and at the same time it reduces the test time significantly for locating those faulty TSVs. Simulation results how that our algorithm achieved up to on an average 33% reduction in test time for a 20 TSV network than serial testing approach. Our algorithm also performs better in terms of est time reduction than the previous work present in the literature.

Through-silicon vias (TSVs) are essential for 3D integrated circuits (ICs) and advanced chiplet packaging. The semiconductor industry is transitioning toward 3D ICs, chiplets, and system-in-package (SiP) solutions due to the slowdown of Moore’s Law and limitations in conventional silicon scaling. In this paper, we propose an optimized TSV architecture for high-frequency transmission to enhance its suitability for 6G communication chips, and develop a comprehensive equivalent circuit model for fault-free and faulty TSVs. This model accounts for open-circuit and short-circuit fault conditions while considering the effects of higher frequencies, substrate type, doping concentration, and adjacent layers. At the physical level, the TSVs are simulated using the Ansys High-Frequency Structure Simulator (HFSS), and the equivalent circuits are designed using the Cadence Virtuoso tool. An experimental evaluation is also conducted to validate the physical design. We position the TSVs in a pattern of ground-signal-ground (G-S-G) to reduce the effective inductance of the signal TSV, thereby minimizing inductive reactance at ultra-high frequencies. Consequently, the reflection coefficient remains below -10 dB across the frequency range of 0.1 to 146.3 GHz. Furthermore, we compare simulation outcomes from HFSS and Cadence for both fault-free and faulty TSVs under varying operating conditions. Additionally, the parasitic circuit components are characterized through extensive theoretical derivations for in-depth circuit verification. Collectively, the rigorous analysis, experimental validation, and thorough investigation of the proposed design and its equivalent circuit demonstrate their potential for use in creating datasets for a fault prediction machine learning model.

In three-dimensional integrated circuit (3D-IC) systems that use through-silicon via (TSV) technology, a significant design consideration is the coupling noise to or from a TSV. It is important to estimate the TSV noise transfer function and manage the noise-tolerance budget in the design of a reliable 3D-IC system. In this paper, a TSV noise coupling model is proposed based on a three-dimensional transmission line matrix method (3D-TLM). Using the proposed TSV noise coupling model, the noise transfer functions from TSV to TSV and TSV to the active circuit can be precisely estimated in complicated 3D structures, including TSVs, active circuits, and shielding structures such as guard rings. To validate the proposed model, a test vehicle was fabricated using the Hynix via-last TSV process. The proposed model was successfully verified by frequency- and time-domain measurements. Additionally, a noise isolation technique in 3D-IC using a guard ring structure is proposed. The proposed noise isolation technique was also experimentally demonstrated; it provided -17 dB and -10dB of noise isolation between the TSV and an active circuit at 100 MHz and 1 GHz, respectively.

The technology of 3D IC integration is highly probable to achieve the demand for high performance, better reliability, miniaturization and lower-priced portable electronic products. Since the through silicon via (TSV) is the heart in 3D IC integration architectures, the reliability issues of TSV interconnects should be extremely concerned. Due to the large thermal expansion mismatch among the Cu, Si, and SiO 2 , the induced thermal stresses and strains can occur and become the driving forces for failures in TSV interconnects. Hence, the stress analyses and failure mode investigation for TSVs are in urgent need. Among the typical failures, the mostly common failure type is delamination, which will be caused when lower energy release rate (ERR) or higher critical stresses at interfaces are presented. In this study, the finite element modeling (FEM) for a symmetrical single in-line copper filled TSV with redistribution layer is illustrated. Two kinds of horizontal cracks that embedded in the interface of SiO 2 passivation and Cu seed layer (Cu pad delamination cases) are introduced to realize the interfacial ERR, where is also the critical stress area that observed from finite element analysis. The significance of design parameters such as crack length, TSV diameter, TSV pitch, depth of TSV, SiO 2 thickness and Cu seed layer thickness are also brought up. The methodology of design of experiments (DoE) has been adopted to capture the most important mechanical parameters of the TSV to comprehend the corresponding ERR. It is believed that these results would be helpful to avoid delamination of TSV interconnects in 3D IC integration.