A 13-bit resolution ROM-less direct digital frequency synthesizer based on a trigonometric quadruple angle formula

A novel design is presented about ROM-less direct digital frequency synthesizer (DDFS) using phase to sinusoid amplitude conversion blocks based on the two segment fourth-order parabolic approximation. The mathematical maximum error analysis shows that the resolution is up to 14 bits. In order to reduce the hardware complexity without sacrificing speed, the squarer and constant multipliers have been decomposed and optimized. The whole architecture has been split into twenty pipelining stages with a 200 MHz clock rate and a single phase output up to 50 MHz. Meanwhile, because the sine and cosine phase to amplitude modules share the same hardware, reduction of hardware complexity and power consumption can be achieved. Spectral purity analysis shows that the worst case spurious free dynamic range (SFDR) is about -90 dBc. The implementation demonstrates that the proposed DDFS architecture can be realized with a smaller hardware scale and lower power consumption than many other existing approaches.

A ROM-less direct digital frequency synthesizer (DDFS) is implemented based on a new 8th-order polynomial approximation of a cosine function, where digital square circuits are used to realize the components of the polynomial. MATLAB tools are used to simulate the performance of the DDFS system, where the spurious free dynamic range (SFDR) is employed as the performance factor. For a DDFS with a superior quality, the higher the SFDR, the better the spectrum purity. To validate the performance of the DDFS, the Altera FPGA platform is used with Quartus II and ModelSim, where simulation results based on Verilog implementation are illustrated.

A pre-realization dynamic power estimation approach for ROM-less direct digital frequency synthesizer (DDFS) designs is proposed, which carries out the analysis of switching activity of all the major logic blocks utilized in the synthesis of ROM-less DDFS. As soon as the partitions of the π/2 and the characteristic equations for polynomial interpolation are given, the proposed approach is able to assess the overall switching activities such that the power profile of different combination of partitions and equations can be derived before any physical implementation.

A 4-stage pipeline ROM-less direct digital frequency synthesizer (DDFS) with equal division interpolation is proposed in this work. To attain higher SFDR (spurious free dynamic range) and faster clock rate, the hardware cost and delay using different segments with various interpolation equations are analyzed systematically to explore the optimal solution. The parabolic equations with proper selection of coefficients and factorized operation orders based on optimized hardware cost and delay are finally utilized to enhance SFDR. The proposed design is demonstrated by the physical implementation on Altera FPGA platform. The average SFDR is measured to be 68.4242 dBc with 1.1659 dBc deviation over 33 times of experiments. The measured SFDR is proved to outperform many previous DDFS works even if they were implemented on silicon.

By using a sine wave Digital-to-Analog Converter (DAC) to perform mapping from digital phase to sine amplitude, the ROM-less Direct Digital Frequency Synthesizer (DDFS) consumes less power than the conventional ROM lookup table approach. To further reduce the power dissipation and the die area of the sine wave DAC, two segmented sine wave DAC architectures are proposed in this paper. The optimized segmentation parameters for better performance and lower power dissipation are also discussed.

This paper presents new techniques to implement direct digital frequency synthesizers (DDFSs) with optimized piecewise-polynomial approximation. DDFS performances with piecewise-polynomial approximation are first analyzed, providing theoretical upperbounds for the spurious-free dynamic range (SFDR), the maximum absolute error, and the signal-to-noise ratio. A novel approach to evaluate, with reduced computational effort, the near optimal fixed-point coefficients which maximize the SFDR is described. Several piecewise-linear and quadratic DDFS are implemented in the paper by using novel, single-summation-tree architectures. The tradeoff between ROM and arithmetic circuits complexity is discussed, pointing out that a sensible silicon area reduction can be achieved by increasing ROM size and reducing arithmetic circuitry. The use of fixed-width arithmetic can be combined with the single-summation-tree approach to further increase performances. It is shown that piecewise-quadratic DDFSs become effective against piecewise-linear designs for an SFDR higher than 100 dBc. Third-order DDFSs are expected to give advantages for an SFDR higher than 180 dBc. The DDFS circuits proposed in this paper compare favorably with previously proposed approaches.

This article discusses the current state and development trends of microwave frequency synthesizers for test-and-measurement instruments. The discussed trends are also applicable for other synthesizer types used as modules in more complex systems. Test-and-measurement synthesizer market is estimated at $300 with an annual growth rate about 3%.A modern trend for the development of frequency synthesizers is associated with low phase noise, low spurious and fast switching speed. Important parameters also include operating frequency range, frequency resolution, modulation capabilities as well as size and cost characteristics. The main architectures based on direct analog, direct digital and indirect synthesis are evaluated. As of today, traditional indirect phase-lock-loop (PLL) architectures still dominate. On the other hand, direct analog synthesis is the most advanced approach that demonstrates extremely fast switching speed and low phase noise. Nevertheless, future developments are associated with direct digital synthesis (DDS) due to the rapid progress in solid-state technologies. DDS are currently available as special integrated circuits (IC) or can be build using field-programmable logic arrays (FPGA) and high-frequency digital-to-analog converters (DAC). Parallel (multichannel) digital structures coupled with high-frequency DACs allow generating output signals at microwave frequencies. Further improvements are possible using two or more DACs in an interleaved data mode. Wider frequency coverage through several tens of gigahertz and lower spur characteristics are expected.The article notes that modern frequency synthesizers allow generating complex signals using vector IQ-modulation. The modulation bandwidth is constantly increases through hundreds of megahertz or even several gigahertz. Further advances in microwave frequency synthesizers are associated with new reference types such as sapphire-loaded cavity oscillators with combined frequency stabilization as well as optoelectronic methods.

Direct Digital Frequency Synthesizer (DDFS) has long been perceived as a predominant solution for producing precise, variable frequency signals having very low distortion. The paper presents an epigrammatic and a comparative study of direct digital frequency synthesizers architectures. The direct digital frequency synthesizer presented are compared on the basis of two architectures namely, the read only memory (ROM) or look up table based architecture and the other co-ordinate rotation based digital computer that eliminates the usage of the large ROM based look up table. These architectures are compared in terms of the power utilization, SFDR, etc. A mixed signal ASIC designing approach is followed for the implementation approach.

This chapter provides a design of micro-broadband radar signal source based on direct digital frequency synthesis technology. This micro-broadband radar signal source is composed of baseband signal source and frequency multiplier chain. Direct Digital Synthesis (DDS) chip AD9858 was used in the baseband signal source. A FPGA chip was employed to load DDS control words to create 200MHz ± 50MHz baseband signal. Multiplier chain achieved up-conversion and frequency doubling of baseband signal, and output 1.5GHz + 400MHz broadband radar Linear Frequency Modulated (LFM) signal. Oscilloscope and spectrum analyzer measurements results showed that the quality of LFM signal met the design requirements.KeywordsExcitation SignalLinear Frequency ModulateBaseband SignalLinear Frequency Modulate SignalFPGA ChipThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

The special driver for tunable F-P filter is expensive, so it has an important application value to design a driver with stable performance and low cost. In this paper, the field programmable gate array (FPGA) was chosen as the core chip to constitute triangular signal generator based on direct digital frequency synthesizer (DDS). The output frequency of waveform ROM look-up table will be altered by changing frequency control word. Then, the products of amplitude word and signals of ROM table output were transmitted to DAC to be converted into analog signal. The variable frequency and amplitude modulation signals were got after smoothed by low pass filter. The frequency range of driving signal is 1 Hz~10 KHz, and the resolution of frequency is 0.1 Hz. The amplitude range is 1 V~10 V, and the resolution of amplitude is 0.1 V. The simulation and experimental results show that the driver has the characteristics of simple structure, stable signal, adjustable frequency and amplitude and lower cost. It can satisfy the requirements of tunable F-P filter driven in practical engineering.

This work presents a low power direct digital frequency synthesizer (DDFS) by using a new two-level lookup table algorithm. The algorithm uses trigonometric double angle formula to divide ROM lookup table into two parts. The ROM size of the proposed architecture is 25% less than that of conventional two-level table. The hardware complexity of the new DDFS architecture compared to the traditional two-level table DDFS can be omitted one multiplier. A synthesized 0.35-mu DDFS with a SFDR of -80dB, runs up to 100MHz and consumes 81-mW at 3.0v. The power efficiency is 0.81-mW/MHz, which represents an enhancement of more than 38% compared to the conventional DDFS

Direct digital frequency synthesizer (referred to as DDS) is a kind of complete digital frequency synthesizer. In this article the principle of DDS were introduced. Set the design index of distortion and resolution, and design parameters of DDS in accordance with the index. DDS design describes by Verilog HDL, implement controlling four parameters of the waveform, frequency, phase, amplitude. Using FPGA and Quartus II/Nios IIwhich is Altera EDA software, realize DDS and its peripheral input / output and DA platform. The final direct to DDS simulation results and the overall DDS platform oscilloscope experimental data, verify the correctness of the design of DDS with the two data.

An 800 MSPS quadrature Direct Digital Frequency Synthesizer (DDFS) with an integrated 13-bit nonlinear DAC and a 200 MHz spur-rejection filter is presented. The system consists of a 10 ns latency ROM-less DDFS and a sine-weighted, current-steering DAC with a layout technique conducive to the DDFS algorithm. A 200 MHz active OTA-RC spur-rejection filter follows the DDFS-DAC giving > 60 dB rejection at 600 MHz with an IIP3 of 25 dBm. The system achieves an SFDR ≈ 33 dB and a total instantaneous hopping time of 15 ns. The system is designed and fabricated in a 0.13 μm CMOS technology, has a total chip area of 2.54 mm × 2.96 mm, and consumes 420 mW of power.

This paper presents a direct digital frequency synthesizer (DDFS) for high speed application based on multichannel structure. This DDFS has phase resolution of 32 bits and magnitude resolution of 12 bits. In order to ensure the high speed and high resolution at the same time, the multi-channel sampling technique is used and a 12 bits linear DAC is implemented. The chip is fabricated in TSMC 130nm CMOS technology with active area of 0.89mm×0.98mm and total power consumption of 300mW at a single 1.2V supply voltage. The maximum operating speed is up to 2.0GHz at room temperature.

This paper describes the design and implementation of a sine-output ROM-less direct digital frequency synthesiser by using a polynomial approximation of which a maximum error less than 2e-4 can be achieved for phase values between 0 to /spl pi//2. The full-period sinewave is generated by using a quadrant-decode technique. This yields a very high spectral purity sinewave output. System-level approximation and experimental results using an FPGA show that the maximum harmonic distortion is less than -67.4 dBc and -64.8 dBc respectively.