A 200-MHz sub-mA RF front end for wireless hearing aid applications

Direct conversion receiver (DCR) architecture is a promising candidate in the radio frequency (RF) front end because of its low power consumption, low cost and ease of integration. However, flicker noise and direct current (DC) offset are large issues. Owing to the local oscillator (LO) frequency, which is half of the RF frequency, and the absence of a DC bias current that introduces no flicker noise, the subharmonic passive mixer (SHPM) core topology front end overcomes the shortcoming effectively. When more and more receivers (RX) and transmitters (TX) are integrated into one chip, the linearity of the receiver front end becomes a very important performer that handles the TX and RX feedthrough. Another reason for the requirement of good linearity is the massive electromagnetic interference that exists in the atmosphere. This paper presents a linearity-improved RF front end with a feedforward body bias (FBB) subharmonic mixer core topology that satisfies modern RF front end demands. A novel complementary derivative superposition (DS) method is presented in low noise amplifier (LNA) design to cancel both the third- and second-order nonlinearities. To the best knowledge of the authors, this is the first time FBB technology is used in the SHPM core to improve linearity. A Volterra series is introduced to provide an analytical formula for the FBB of the SHPM core. The design was fabricated in a 0.13 μm complementary metal oxide semiconductor (CMOS) process with a chip area of 750 μm × 1270 μm. At a 2.4 GHz working frequency, the measurement result shows a conversion gain of 36 dB, double side band (DSB) noise figure (NF) of 6.8 dB, third-order intermodulation intercept point (IIP3) of 2 dBm, LO–RF isolation of 90 dB and 0.8 mW DC offset with 14.4 mW power consumption at 1.2 V supply voltage. These results exhibit better LO–RF feedthrough and DC offset, good gain and NF, moderate IIP3 and the highest figure of merit compared to the state-of-the-art publications.

A frequency-modulated ultrawideband (FM-UWB) hybrid transceiver, with a high system reuse ratio up to 90%, is fabricated in the 65-nm CMOS process for both short-range wireless communication and high-resolution radar ranging. The radio frequency (RF) front-ends (RFFEs) based on module stacking and current reuse achieve significant RF power savings of about 30% and 50% for the transmitter and the receiver (RX), respectively. The presented IF zero-crossing delay discrimination benefits a high radar resolution less than 1 cm. A multimode relaxation oscillator (OSC) for the reconfigured triangular subcarrier generation and a dual-path ring voltage-controlled oscillator (VCO) for the linear FM, stacked by a wideband push–pull power amplifier (PA), generate an FCC-compliant UWB signal. An active balun embedded low-noise amplifier (LNA) and two symmetric-detuning band-passed filters (BPFs) are stacked with the bandwidth extension to linearly demodulate the UWB FM signal. Experimental results show that the 3.75–4.25-GHz hybrid transceiver has an energy efficiency of 1.9 nJ/bit with an active area of 0.7 mm2 and a power dissipation of 1.9 mW and achieves the RX sensitivity of −71 dBm and the transmitted power of −14.1 dBm, with a bit error rate (BER) of 10−4 at a distance of 4 m under the data rate (DR) of 0.1–1.0 Mbps. The transceiver also achieves the noise figure (NF) of 4.8 dB and the phase noise of −78.6 dBc/Hz at 1-MHz offset frequency.

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

Microwave integrated systems in silicon provide a low cost, low power and high yield solution for wideband data communication, radar, and many other applications. Phased-array systems are capable of steering the radiation beam by electronic means, emulating the behavior of a directional antenna. This dissertation is dedicated to presenting various techniques to implement microwave integrated phased-array receivers in silicon-based technologies in the context of three design examples. A 24-GHz 0.18-µm complementary metal oxide semiconductor (CMOS) front-end was demonstrated. The front-end consists of a low noise amplifier (LNA) and a mixer. The LNA utilizes a novel topology common-gate with resistive feedthrough to obtain low-noise performance. The entire front-end achieves a 7.7dB noise figure and a 27.5dB power gain. A fully integrated 8-element 24-GHz silicon germanium (SiGe) phased array receiver was implemented. The receiver uses two-step downconversion and local oscillator (LO) phase shifting with 4-bit resolution. The signal is combined at the 4.8-GHz intermediate frequency. The 16 phases of 19.2-GHz LO signal are generated with a voltage controlled oscillator (VCO) and symmetrically distributed to the phase selectors at all path. Appropriate phase sequence is applied to the phase distribution transmission lines to minimize mismatch. An integrated frequency synthesizer locks the 19.2-GHz VCO output to a 75-MHz external reference. Measured array patterns show a peak-to-null ratio of more than 20dB and a beam steering range covering all signal incident angles. An integrated 4-element 77-GHz SiGe wideband phased-array transceiver was implemented. Two-step conversion is used at both the receiver and the transmitter. A differential phase of 52 GHz is generated by the VCO and distributed to all RF paths at the transmitter and receiver. The phase shifting is performed at the LO ports of the RF mixers using continuous analog phase shifters. The quadrature signal of the second LO frequency is generated by dividing the VCO frequency by a factor of 2 using a cross-coupled injection-locked frequency divider. The signal combining is performed at IF with an active combining amplifier. The receiver achieves a 41dB gain at 80 GHz with 3 GHz of bandwidth. The 52-GHz-to-50MHz frequency divider chain obtains 7% locking range.

A low-power fully integrated wideband low noise amplifier (LNA) and down-conversion mixer are designed for direct sequence-UWB (DS-UWB) RF front-end using 0.18-μm CMOS technology. The LNA is designed to cover the full UWB bandwidth of 7.5GHz. Measurements show this LNA achieves gain of 14 16.5dB, noise figure (NF) of 4.2 - 4.8dB and IIP3 of -8dBm, consuming 6mA of current from a 1.8-V supply. The mixer is designed using Gilbert-cell topology to work for both DS-UWB bands. Over both bands, the mixer achieves voltage gain of 4 - 6dB, IIP3 of -1dBm, and NF of 14 to 18dB with a supply current of 11.5mA from a 1.8-V supply.

This paper presents the design and simulation of a 60GHz low noise amplifier (LNA) using 40nm CMOS technology for millimeter-waves (MMW) wireless communication applications. A regulated cascode (RGC) topology is adopted to improve the gain and noise performance of the LNA. Simulated results show that the proposed LNA achieves a power gain of 10.4dB and a noise figure (NF) of 5.8dB at 60GHz. The 3dB bandwidth is 6GHz from 56GHz to 62GHz, and the NF is less than 6.4dB across the entire band. The whole circuit consumes 12.2mW with a 1.1V supply. To the author's knowledge, the proposed LNA achieves quite a low power consumption while having such a gain and NF at 60GHz.

This paper presents a high-gain, dual-band low noise amplifier (LNA) for 5G wireless systems, which supports simultaneous operation at 28 GHz and 38 GHz. The circuit consists of two cascode stages, and is implemented in a 22 nm FD-SOI CMOS technology. To realize the dual-band operation, dual-band matching networks based on transmission lines and capacitors were used. The presented LNA draws a current of 7.1 mA from a 1.6 V supply, which results in a total power consumption of 11.4 mW. The LNA provides a gain of 19.3 dB and 24 dB at 28 GHz and 38 GHz, respectively. At the input of the LNA a dual-band matching network was implemented to obtain a simultaneous noise and power matching at 28 GHz and 38 GHz. The measured noise figure at 28 GHz and 38 GHz is about 5 dB. The presented LNA compares well against previously reported designs by showing one of the highest gain and the lowest power consumption while still having the comparable performance in the other figures of merit. To the best knowledge of the authors, this is the first LNA using dual-band matching technique to support dual-band operation at 5G millimeter-wave bands.

In this paper, a low-power ultra-wideband low noise amplifier (LNA) is presented. The combination of dual resonance network and current-bleeding technique offers high and flat voltage gain and low noise figure (NF), and also, the gain-controller resistor technique causes better control of voltage gain to achieve flatter gain. Furthermore, the CS–CD (Common-Source Common-Drain) current-reuse technique provides output return loss reduction and eliminates buffer stage in LNA design. It has been shown that using this scheme, noticeable improvement has been obtained in the frequency range of 2–11 GHz. This improvement consists of minimum noise figure value as 2.5 dB, the maximum value of 4.2 dB and average noise figure lower than 3 dB in a wide frequency range, from 4 to 10 GHz. The proposed LNA achieves the average voltage gain of 12.35 dB with a variation of 0.85 dB in the frequency range of 2–11 GHz. Input and output return losses are below − 10 dB and IIP3 of the proposed structure is − 3 dBm. The proposed LNA consumes 9.52 mW in 1-V supply voltage. Moreover, the size of the structure is 0.54 mm2 in TSMC 180-nm technology.

The life time of RF front end in wireless sensor networks (WSN) is so important that it decides whether the whole system can work normally for a long time. Under CMOS technology, negative bias temperature instability (NBTI) is one of the most important factors that decide chips' life time. Especially with the feature size declining, NBTI effect is becoming more and more serious. Previous works mainly focus on NBTI effect at device level, or NBTI effect in large-scale digital circuits. In this paper, for the WSN node, we study the NBTI impact on the front- end circuits, such as voltage-controlled oscillators (VCO), charge pump (CP), low noise amplifier (LNA), and the whole transceiver system. The circuit level NBTI degeneration models are built for the key modules and the entire transceiver. The mathematical models can be summarized into a conclusion that the phase noise of the VCO will deteriorate, the current mismatch of the CP and the noise figure of the LNA will both increase, and then the sensitivity and adjacent channel selectivity (ACS) will be depressed by NBTI. Under HJTC 0.18-mum technology, our conclusions are proved by the simulation results.

A low-power, 1.57 GHz RF front-end for a Global Positioning System (GPS) receiver has been designed in a 1.0 /spl mu/m BiCMOS technology. It consists of a low noise amplifier with 15 dB of gain, a single balanced mixer with 6.3 mS of conversion g/sub m/, a Colpitts LC local oscillator, and an emitter coupled logic (ECL) divide-by-eight prescaler. This front-end has a single sideband (SSB) noise figure of 8.1 dB and is part of a triple conversion superheterodyne receiver whose IF frequencies are 179, 4.7, and 1.05 MHz. Low power consumption has been achieved, with 10.5 mA at 3 V supply voltage for the front-end, while the complete receiver is expected to draw about 12 mA.

In this paper, a high gain 77-GHz receiver with a low noise figure (NF) was designed and implemented in a 40-nm CMOS process. With the purpose of making better use of active devices, an extra inductor, Ld, is adopted in the new neutralization technique. The three-stage differential low noise amplifier (LNA) using the proposed technique improves the voltage gain and reduces the NF. The receiver design utilizes an active double-balanced Gilbert mixer with a transformer coupling network between the transconductance stage and the switch stage. The flicker noise contribution from the switch MOS transistors is largely reduced due to the low DC current of the switch pairs. The LO signal is provided by an on-chip fundamental voltage-controlled oscillator (VCO) with a tuning range from 70.5 to 78.1 GHz. A conversion gain of 32 dB and a NF of 11.86 dB are achieved at 77 GHz by the designed receiver. The LNA as well as the mixer consume a total DC power of 33.2 mW and occupy a core size of 1 × 0.38 mm2.

The effects of packaging in inductively degenerated common-source low-noise amplifiers (LNAs) with electrostatic discharge (ESD) protection are studied and the performance of the packaged LNA is optimized. Equations describing the input impedance, transconductance, voltage gain, and noise figure (NF) of the packaged amplifier are derived and the effects of the LNA input matching network, package, and ESD parasitics on these amplifier quantities are highlighted. From the equations, several design guidelines for the packaged LNA are obtained and a systematic approach for the ESD-protected LNA optimization is deduced. It is also shown that, in the presence of an equivalent parallel package parasitic capacitance C/sub p/, the NF in a well-optimized LNA is easily dominated by the losses of the input-matching network instead of the active device noise. Based on the theoretical results, a packaged inductively degenerated common-source LNA with ESD protection is designed in a 0.13-/spl mu/m CMOS process. The amplifier provides a forward gain (S/sub 21/) of almost 18 dB at 2 GHz with an NF of 1.6 dB while consuming 8.4 mW from a 1.2-V supply.

This paper presents a new design of inductorless wideband front-end receiver using 130 nm CMOS technology for LTE bands of 0.7 GHz to 3 GHz. The RF front-end receiver consists of the microstrip antenna, self-bias resistive feedback low-noise amplifier, active balun and folded mixer architecture. The miniature antenna provides good matching results for the entire band of interest. Optimization of low-noise amplifier using linearization technique followed by NMOS switches mixer stage are effectively used to achieve maximum gain, low noise figure, and low power consumption. The designed receiver exhibits a maximum gain of 22 dB, maximum noise figure of 7.5 dB, minimum 3rd order intercept point (IIP3) of −9.2 dBm, and DC power consumption of 22 mW at 1.2 V power supply. Using these optimizations, our proposed receiver can be a good candidate for LTE applications.

This paper presents a low power Gaussian Frequency-Shift Keying (GFSK) transceiver (TRX) with high efficiency power management unit and integrated Single-Pole Double-Throw switch for Bluetooth low energy application. Receiver (RX) is implemented with the RF front-end with an inductor-less low-noise transconductance amplifier and 25% duty-cycle current-driven passive mixers, and low-IF baseband analog with a complex Band Pass Filter(BPF). A transmitter (TX) employs an analog phase-locked loop (PLL) with one-point GFSK modulation and class-D digital Power Amplifier (PA) to reduce current consumption. In the analog PLL, low power Voltage Controlled Oscillator (VCO) is designed and the automatic bandwidth calibration is proposed to optimize bandwidth, settling time, and phase noise by adjusting the charge pump current, VCO gain, and resistor and capacitor values of the loop filter. The Analog Digital Converter (ADC) adopts straightforward architecture to reduce current consumption. The DC-DC buck converter operates by automatically selecting an optimum mode among triple modes, Pulse Width Modulation (PWM), Pulse Frequency Modulation (PFM), and retention, depending on load current. The TRX is implemented using 1P6M 55-nm Complementary Metal–Oxide–Semiconductor (CMOS) technology and the die area is 1.79 mm2. TRX consumes 5 mW on RX and 6 mW on the TX when PA is 0-dBm. Measured sensitivity of RX is −95 dBm at 2.44 GHz. Efficiency of the DC-DC buck converter is over 89% when the load current is higher than 2.5 mA in the PWM mode. Quiescent current consumption is 400 nA from a supply voltage of 3 V in the retention mode.

In this paper, a Ku-band LNA at 13– 16 GHz is designed with low NF, high gain, and low power consumption for space application This paper presents high gain, too low noise figure, and low power consumption low noise amplifier (LNA). Simultaneously achieving high gain and low noise figure (NF), a popular source degeneration technique is used. Also for achieving high gain, this work is implemented with three-stage cascade source degeneration technique. The proposed work also aims to optimize the input, output and isolation losses. For achieving a low noise figure, InGaAs HEMT technology is used and Ku Band at 13–16 GHz LNA is designed for space application. Simulated results are NF of 1.008 and 0.719 dB and gain of 29.70 and 22.83 dB. The less than −12 dB is achieved for return losses of input and output. The Stability Factor and Mu1 are greater than 3 at desired 13–16 GHz. The amplifier biasing V ds , I ds is 2V and 10 mA respectively are chosen. The Keysight Technology Advanced Design System is used for simulating all parameters. The LNA consumes the power of 250 mW from the simulated values.