Low-Power Low-Complexity FM-UWB Hybrid Transceiver for Communication and Ranging

Rapidly growing demand for high data rates in wireless communication systems is the cause of the merging of Multiple Input Multiple Output (MIMO) and Orthogonal Frequency Division Multiplexing (OFDM) techniques. MIMO-OFDM technique needs Radio Frequency (RF) front end in each antenna, which is not effective for large dimensional antenna size. Therefore, RF front end on the receiver side will be simplified using a single RF technique based on the Electrically Steerable Parasitic Array Radiator (ESPAR) antenna. In real life, a channel cannot be ideal. Therefore, before the signal is transmitted, that signal must be coded to minimized errors when the data transmission process. Convolutional code is a coding technique that can detect and correct error bit (error control coding) and that it is expected to reduce the quantity of Bit Error Rate (BER). In this research, a simulation is designed to analyze single RF performance on the MIMO-OFDM system using Vertical Bell Laboratories Space-Time (VBLAST) detection for convolutional code encoder and Viterbi decoder. The result simulation shows that the channel estimation technique works well on the MIMO-OFDM system using single RF, which is shown in the magnitude and phase curves against the subcarrier index between the theory channel and the estimated channel are at almost the same points. VBLAST-ZF detector performance is shown in the BER curve against SNR, where the difference BER value for SNR value 10 dB between the theory channel and the estimated channel is 0.001499. Channel coding technique using convolutional code encoder and Viterbi decoder with a rate of ½ works well on the MIMO-OFDM system using single RF which is shown in the BER curve against SNR, where BER value with coding technique is smaller than BER value without coding technique.

Direct conversion receiver (DCR) architecture is a promising candidate in the radio frequency (RF) front end because of its low power consumption, low cost and ease of integration. However, flicker noise and direct current (DC) offset are large issues. Owing to the local oscillator (LO) frequency, which is half of the RF frequency, and the absence of a DC bias current that introduces no flicker noise, the subharmonic passive mixer (SHPM) core topology front end overcomes the shortcoming effectively. When more and more receivers (RX) and transmitters (TX) are integrated into one chip, the linearity of the receiver front end becomes a very important performer that handles the TX and RX feedthrough. Another reason for the requirement of good linearity is the massive electromagnetic interference that exists in the atmosphere. This paper presents a linearity-improved RF front end with a feedforward body bias (FBB) subharmonic mixer core topology that satisfies modern RF front end demands. A novel complementary derivative superposition (DS) method is presented in low noise amplifier (LNA) design to cancel both the third- and second-order nonlinearities. To the best knowledge of the authors, this is the first time FBB technology is used in the SHPM core to improve linearity. A Volterra series is introduced to provide an analytical formula for the FBB of the SHPM core. The design was fabricated in a 0.13 μm complementary metal oxide semiconductor (CMOS) process with a chip area of 750 μm × 1270 μm. At a 2.4 GHz working frequency, the measurement result shows a conversion gain of 36 dB, double side band (DSB) noise figure (NF) of 6.8 dB, third-order intermodulation intercept point (IIP3) of 2 dBm, LO–RF isolation of 90 dB and 0.8 mW DC offset with 14.4 mW power consumption at 1.2 V supply voltage. These results exhibit better LO–RF feedthrough and DC offset, good gain and NF, moderate IIP3 and the highest figure of merit compared to the state-of-the-art publications.

In mobile and portable wireless devices, it is important to have low power dissipation so as to maximize battery life. As the overall power dissipation of a device is dominated by the radio frequency (RF) front end rather than the digital circuit, low-power RF front end design has become a very hot topic in both research and implementation. In this paper, we propose a design method to minimize the power dissipation of a RF front end. Specifically, given the overall specifications of gain, linearity and noise figure of a front end, we derive the optimal specification for each building block of the RF front end such that the overall power dissipation is minimized. By using a specific example of a front end consisting of a couple of cascaded circuit blocks using 90nm CMOS technology, we demonstrate that significant reduction in power dissipation can be achieved using the proposed design method.

This paper discusses use of MEMS technologies in radio frequency (RF) frontend. First, configuration of RF front-end in current wireless communication systems is surveyed, and research trends of the flexible RF front-end and software defined radio (SDR) are discussed. Second, various RF tunable filters are introduced, and we discuss how high performances are expected by the use of tunable RF surface and bulk acoustic wave (SAW/BAW) filters provided that above mentioned key technologies are developed. Finally, our attempts for realization of tunable RF SAW/BAW filters are introduced.

A hearing-aid system with RF connection between both ear-pieces is described and its transceiver is introduced. A suitable 200-MHz RF front end has been implemented in a 0.8-/spl mu/m BiCMOS technology. Low power consumption and area constraint were key requirements. The chip comprises a low noise amplifier (LNA), a single balanced mixer, a varactor tuned LC local oscillator with buffer and a 16/17 dual-modulus prescaler. The LNA has a measured gain of 17.5 dB at 200 MHz. The conversion g/sub m/ of the mixer is 1.88 mS. The overall voltage gain and noise figure are 26 dB and 5.2 dB, respectively. The voltage-controlled oscillator's (VCO's) phase noise is -104.7 dBc/Hz at an offset of 24 kHz.

Application of high-temperature superconducting small current limiting against over-current in low-noise amplifier electronic circuit

Polarization-sensitive array (PSA) can sense satellite signals from multiple dimensions and separate signals from interference according to various characteristics. Hence, the use of PSA improves the interference rejection capability of the global navigation satellite system (GNSS). Whereas it also brings a significant increase in computational complexity as there are more dimensions of array signal processing. Therefore, it is urgent to seek a method to employ fewer radiofrequency (RF) front-ends and antennas while still achieving superior anti-interference performance. In this paper, we investigate the influence of PSA configuration on interference suppression performance and propose an RF front-end optimal selection scheme for reconfigurable anti-jamming PSA with application to GNSS. Combining adaptive array processing algorithm and RF front-end selection strategy, we formulate the expression of the effective carrier to noise ratio (CNR) to analyze the performance enhancement generated by PSA reconfiguration. An approach is presented to solve the upper bound of the effective CNR to plot the trade-off curve between performance and cost, which can guide the selection of the optimal number of RF front-ends. Then another method is used to acquire the layout of the chosen optimal RF front-ends that can maximize the effective CNR. Numerical results illustrate the effectiveness and high efficiency of the proposed PSA reconfiguration scheme.

Multi-band RF front-ends with adaptive image rejection : a DECT/Bluetooth study case

At 60 GHz, millimeter wave circuit design a great gain and small noise figure (NF) is preferable at radio frequency front end. Broad bandwidth is preferred over wireless personal area network and radio detection and ranging. The necessities of a recipient front-end join extraordinary data and yield impedance organizing, high port-to-port separation, low clamor, and high increase over the whole band of intrigue. These requirements are satisfied by the proposed Low-Noise Amplifier design. Conversion gain (S$$_{21})$$ of 11.289 dB, NF of 1.819 dB, the stability of 2.167, Bandwidth of 16.5 GHz are achieved. Also, input and output replication factors are S$$_{11}$$ = − 12.148 dB and S$$_{22}$$ = − 12.238 dB. Impedance matching has finished by transmission lines. Propelled design system has utilized for pre-format and post-format simulation. Low Noise Amplifier is implemented in 180 nm CMOS development. As compared with other traditional strategies the proposed ADS is achieved low power utilization of 7.25 mW from a 1.5 V supply and it accomplishes a voltage achievement of 12 dB, 3-dB bandwidth of 60 GHz.

In this paper, a wideband CMOS radio frequency (RF) front-end for digital video broadcasting-handheld (DVB-H) receiver is proposed. The RF front-end circuit is composed of a single-ended resistive feedback low noise amplifier (LNA), a single-to-differential amplifier, an I/Q down-conversion mixer with linearized transconductors employing third order intermodulation distortion cancellation, and a divide-by-two circuit with LO buffers. By employing a third order intermodulation (IMD3) cancellation technique and vertical NPN bipolar junction transistor (BJT) switching pair for an I/Q down-conversion mixer, the proposed RF front-end circuit has high linearity and low low-frequency noise performance. It is fabricated in a 0.18µm deep n-well CMOS technology and draws 12mA from a 1.8V supply voltage. It shows a voltage gain of 31dB, a noise figure (NF) lower than 2.6dB, and an IIP3 of -8dBm from 470MHz to 862MHz.

This paper presents a highly linear radio frequency front end (RFFE) receiver (Rx) with its frequency response characterized by having an adjustable shape, center frequency, and bandwidth (BW). The RFFE Rx output is sampled at an adjustable sampling rate to be fed to an ADC for further baseband processing. The architecture employs a generalization of noise cancelling theory to reduce the noise figure (NF) by including an auxiliary path besides its main path to be able to subtract the noise at the output. Simulated on 65 nm technology, this method is proved to reduce the NF from 6.5 dB to 3.5 dB for a selected filter impulse response and down to 2.3 dB in case of implementing a Sinc frequency response.

The life time of RF front end in wireless sensor networks (WSN) is so important that it decides whether the whole system can work normally for a long time. Under CMOS technology, negative bias temperature instability (NBTI) is one of the most important factors that decide chips' life time. Especially with the feature size declining, NBTI effect is becoming more and more serious. Previous works mainly focus on NBTI effect at device level, or NBTI effect in large-scale digital circuits. In this paper, for the WSN node, we study the NBTI impact on the front- end circuits, such as voltage-controlled oscillators (VCO), charge pump (CP), low noise amplifier (LNA), and the whole transceiver system. The circuit level NBTI degeneration models are built for the key modules and the entire transceiver. The mathematical models can be summarized into a conclusion that the phase noise of the VCO will deteriorate, the current mismatch of the CP and the noise figure of the LNA will both increase, and then the sensitivity and adjacent channel selectivity (ACS) will be depressed by NBTI. Under HJTC 0.18-mum technology, our conclusions are proved by the simulation results.

A low-power fully integrated wideband low noise amplifier (LNA) and down-conversion mixer are designed for direct sequence-UWB (DS-UWB) RF front-end using 0.18-μm CMOS technology. The LNA is designed to cover the full UWB bandwidth of 7.5GHz. Measurements show this LNA achieves gain of 14 16.5dB, noise figure (NF) of 4.2 - 4.8dB and IIP3 of -8dBm, consuming 6mA of current from a 1.8-V supply. The mixer is designed using Gilbert-cell topology to work for both DS-UWB bands. Over both bands, the mixer achieves voltage gain of 4 - 6dB, IIP3 of -1dBm, and NF of 14 to 18dB with a supply current of 11.5mA from a 1.8-V supply.

Circuit requirements of a direct-conversion FLEX paging receiver with the zero-crossing interpolation demodulator are derived by means of high-level simulation. Impacts of the limitations on noise and nonlinearity characteristics of the radio frequency (RF) stage, the in-phase and quadrature-phase mismatch, and the local oscillator frequency drift are analyzed relative to the degradation of the bit error rate. Official specifications on radio paging receivers are introduced to ensure the minimum performance. It is shown that an RF front end with 25-dB gain, 5.3-dB noise figure, and 11-dBm second order intercept point makes the receiver qualified for the sensitivity, desensitization, and intermodulation requirements.

Planar Beam-forming Antenna Array for 60-GHz Broadband Communication