Circuit requirements of a direct conversion paging receiver

Direct conversion receiver (DCR) architecture is a promising candidate in the radio frequency (RF) front end because of its low power consumption, low cost and ease of integration. However, flicker noise and direct current (DC) offset are large issues. Owing to the local oscillator (LO) frequency, which is half of the RF frequency, and the absence of a DC bias current that introduces no flicker noise, the subharmonic passive mixer (SHPM) core topology front end overcomes the shortcoming effectively. When more and more receivers (RX) and transmitters (TX) are integrated into one chip, the linearity of the receiver front end becomes a very important performer that handles the TX and RX feedthrough. Another reason for the requirement of good linearity is the massive electromagnetic interference that exists in the atmosphere. This paper presents a linearity-improved RF front end with a feedforward body bias (FBB) subharmonic mixer core topology that satisfies modern RF front end demands. A novel complementary derivative superposition (DS) method is presented in low noise amplifier (LNA) design to cancel both the third- and second-order nonlinearities. To the best knowledge of the authors, this is the first time FBB technology is used in the SHPM core to improve linearity. A Volterra series is introduced to provide an analytical formula for the FBB of the SHPM core. The design was fabricated in a 0.13 μm complementary metal oxide semiconductor (CMOS) process with a chip area of 750 μm × 1270 μm. At a 2.4 GHz working frequency, the measurement result shows a conversion gain of 36 dB, double side band (DSB) noise figure (NF) of 6.8 dB, third-order intermodulation intercept point (IIP3) of 2 dBm, LO–RF isolation of 90 dB and 0.8 mW DC offset with 14.4 mW power consumption at 1.2 V supply voltage. These results exhibit better LO–RF feedthrough and DC offset, good gain and NF, moderate IIP3 and the highest figure of merit compared to the state-of-the-art publications.

A frequency-modulated ultrawideband (FM-UWB) hybrid transceiver, with a high system reuse ratio up to 90%, is fabricated in the 65-nm CMOS process for both short-range wireless communication and high-resolution radar ranging. The radio frequency (RF) front-ends (RFFEs) based on module stacking and current reuse achieve significant RF power savings of about 30% and 50% for the transmitter and the receiver (RX), respectively. The presented IF zero-crossing delay discrimination benefits a high radar resolution less than 1 cm. A multimode relaxation oscillator (OSC) for the reconfigured triangular subcarrier generation and a dual-path ring voltage-controlled oscillator (VCO) for the linear FM, stacked by a wideband push–pull power amplifier (PA), generate an FCC-compliant UWB signal. An active balun embedded low-noise amplifier (LNA) and two symmetric-detuning band-passed filters (BPFs) are stacked with the bandwidth extension to linearly demodulate the UWB FM signal. Experimental results show that the 3.75–4.25-GHz hybrid transceiver has an energy efficiency of 1.9 nJ/bit with an active area of 0.7 mm2 and a power dissipation of 1.9 mW and achieves the RX sensitivity of −71 dBm and the transmitted power of −14.1 dBm, with a bit error rate (BER) of 10−4 at a distance of 4 m under the data rate (DR) of 0.1–1.0 Mbps. The transceiver also achieves the noise figure (NF) of 4.8 dB and the phase noise of −78.6 dBc/Hz at 1-MHz offset frequency.

Rapidly growing demand for high data rates in wireless communication systems is the cause of the merging of Multiple Input Multiple Output (MIMO) and Orthogonal Frequency Division Multiplexing (OFDM) techniques. MIMO-OFDM technique needs Radio Frequency (RF) front end in each antenna, which is not effective for large dimensional antenna size. Therefore, RF front end on the receiver side will be simplified using a single RF technique based on the Electrically Steerable Parasitic Array Radiator (ESPAR) antenna. In real life, a channel cannot be ideal. Therefore, before the signal is transmitted, that signal must be coded to minimized errors when the data transmission process. Convolutional code is a coding technique that can detect and correct error bit (error control coding) and that it is expected to reduce the quantity of Bit Error Rate (BER). In this research, a simulation is designed to analyze single RF performance on the MIMO-OFDM system using Vertical Bell Laboratories Space-Time (VBLAST) detection for convolutional code encoder and Viterbi decoder. The result simulation shows that the channel estimation technique works well on the MIMO-OFDM system using single RF, which is shown in the magnitude and phase curves against the subcarrier index between the theory channel and the estimated channel are at almost the same points. VBLAST-ZF detector performance is shown in the BER curve against SNR, where the difference BER value for SNR value 10 dB between the theory channel and the estimated channel is 0.001499. Channel coding technique using convolutional code encoder and Viterbi decoder with a rate of ½ works well on the MIMO-OFDM system using single RF which is shown in the BER curve against SNR, where BER value with coding technique is smaller than BER value without coding technique.

In mobile and portable wireless devices, it is important to have low power dissipation so as to maximize battery life. As the overall power dissipation of a device is dominated by the radio frequency (RF) front end rather than the digital circuit, low-power RF front end design has become a very hot topic in both research and implementation. In this paper, we propose a design method to minimize the power dissipation of a RF front end. Specifically, given the overall specifications of gain, linearity and noise figure of a front end, we derive the optimal specification for each building block of the RF front end such that the overall power dissipation is minimized. By using a specific example of a front end consisting of a couple of cascaded circuit blocks using 90nm CMOS technology, we demonstrate that significant reduction in power dissipation can be achieved using the proposed design method.

This paper discusses use of MEMS technologies in radio frequency (RF) frontend. First, configuration of RF front-end in current wireless communication systems is surveyed, and research trends of the flexible RF front-end and software defined radio (SDR) are discussed. Second, various RF tunable filters are introduced, and we discuss how high performances are expected by the use of tunable RF surface and bulk acoustic wave (SAW/BAW) filters provided that above mentioned key technologies are developed. Finally, our attempts for realization of tunable RF SAW/BAW filters are introduced.

Multi-band RF front-ends with adaptive image rejection : a DECT/Bluetooth study case

This paper demonstrates a system level design of a Cognitive Radio (CR) receiver that supports IEEE 802.22 Standard. In this work, we put a special interest on the impact of adaptive modulation on the design of the Radio Frequency (RF) receiver Front-End. Its architecture is based on super-heterodyne receiver supporting Sub-Band Sensing technique. In this study, the IEEE 802.22 radio system characteristics are dispatched throughout the different RF receiver blocks. Besides, theoretical computation and various techniques of the system level design are developed. Simulation results for RF characteristics such as noise figure (NF), linearity (third order intercept point, (IIP3)), gain, and output power are introduced. The obtained specifications for each RF block proved that its linearity and NF requirements are related to its own gain performance. The receiver performs a total gain of 54dB and an IIP3 of −17.8dBm for low gain mode. It achieves 105dB as gain, IIP3 of −23.7dBm and a noise figure of 6.6dB for high gain mode.

Polarization-sensitive array (PSA) can sense satellite signals from multiple dimensions and separate signals from interference according to various characteristics. Hence, the use of PSA improves the interference rejection capability of the global navigation satellite system (GNSS). Whereas it also brings a significant increase in computational complexity as there are more dimensions of array signal processing. Therefore, it is urgent to seek a method to employ fewer radiofrequency (RF) front-ends and antennas while still achieving superior anti-interference performance. In this paper, we investigate the influence of PSA configuration on interference suppression performance and propose an RF front-end optimal selection scheme for reconfigurable anti-jamming PSA with application to GNSS. Combining adaptive array processing algorithm and RF front-end selection strategy, we formulate the expression of the effective carrier to noise ratio (CNR) to analyze the performance enhancement generated by PSA reconfiguration. An approach is presented to solve the upper bound of the effective CNR to plot the trade-off curve between performance and cost, which can guide the selection of the optimal number of RF front-ends. Then another method is used to acquire the layout of the chosen optimal RF front-ends that can maximize the effective CNR. Numerical results illustrate the effectiveness and high efficiency of the proposed PSA reconfiguration scheme.

This paper presents a highly linear radio frequency front end (RFFE) receiver (Rx) with its frequency response characterized by having an adjustable shape, center frequency, and bandwidth (BW). The RFFE Rx output is sampled at an adjustable sampling rate to be fed to an ADC for further baseband processing. The architecture employs a generalization of noise cancelling theory to reduce the noise figure (NF) by including an auxiliary path besides its main path to be able to subtract the noise at the output. Simulated on 65 nm technology, this method is proved to reduce the NF from 6.5 dB to 3.5 dB for a selected filter impulse response and down to 2.3 dB in case of implementing a Sinc frequency response.

The main limitation of using a multiple antenna architecture is the complexity and high cost of the hardware in the radio frequency (RF) section, which rise with an increase in the number of antennas. In addition, RF circuit mismatches [1-3] and coupling [4] grow with an increase in the number of antennas; consequently, these factors also limit the use of high numbers of antennas at the transceiver.One solution to compensate for the extra hardware cost and RF circuit imperfection is the utilization of a single RF front-end in a multiple input multiple output (MIMO) system, where a single RF path is used instead of multiple parallel RF paths. This results in an RF section that has lower complexity and cost, a simpler RF design, a compact size, and lower power consumption.A conventional MIMO receiver with N antennas at the receiver is shown in Figure 10.1. The receiver uses multiple parallel RF front-ends, where the number of RF front-ends is equal to the number of antennas. In this architecture, the baseband processing section decodes N received baseband paths to recover the signal and obtain the diversity or spatial multiplexing gain. To realize a single RF frontend path, orthogonal transmission of multiple RF streams over a single front-end must be recognized. In the following subsections, the different techniques to realize a single RF front-end in a MIMO system are discussed.KeywordsRadio FrequencyAntenna SelectionRadio Frequency CircuitRadio Frequency TransceiverSingle Radio FrequencyThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

In this paper, a wideband CMOS radio frequency (RF) front-end for digital video broadcasting-handheld (DVB-H) receiver is proposed. The RF front-end circuit is composed of a single-ended resistive feedback low noise amplifier (LNA), a single-to-differential amplifier, an I/Q down-conversion mixer with linearized transconductors employing third order intermodulation distortion cancellation, and a divide-by-two circuit with LO buffers. By employing a third order intermodulation (IMD3) cancellation technique and vertical NPN bipolar junction transistor (BJT) switching pair for an I/Q down-conversion mixer, the proposed RF front-end circuit has high linearity and low low-frequency noise performance. It is fabricated in a 0.18µm deep n-well CMOS technology and draws 12mA from a 1.8V supply voltage. It shows a voltage gain of 31dB, a noise figure (NF) lower than 2.6dB, and an IIP3 of -8dBm from 470MHz to 862MHz.

Strong current response is always induced according to the antennas with the operating frequency below 300MHz exposed to High-altitude electromagnetic pulse (HEMP), which may cause severe damages of radio frequency (RF) sub-system by entering into the core RF integrated circuit (IC) components or devices along the RF front-end channel step by step. In order to monitor the transient response of each RF component port in front-end channel, an open VHF communication system is designed. Based on this system, we observe the transient response of all key RF IC components along receiving channel by using pulsed conducted injection (PCI) test respectively. Finally, necessary performance test and effect mechanism analysis are made after PCI tests. The experimental results illustrates a series of interesting conclusions for further study on HEMP effect mechanism research and protection design of the RF front-end subsystems.

Direct-conversion radio transceivers can offer reprogrammable and low-cost hardware solutions for full-duplex (FD) cognitive radio (CR) devices. However, they are susceptible to radio frequency (RF) impairments, such as in-phase (I) and quadrature (Q) imbalance (IQI), which can significantly constrain the spectrum sensing capabilities. This paper is devoted to quantify and evaluate the effects of IQI in the context of spectrum sensing in FD CR systems, in which self-interference suppression (SIS) techniques are employed. Specifically, closed form expressions are derived for the false alarm and detection probabilities, under three different scenarios: imperfect SIS with joint transmitter (TX) and receiver (RX) IQI, imperfect SIS and ideal TX/RX RF front-end, and perfect SIS and ideal TX/RX RF front-end. The derived analytical results are validated through extensive simulations, which reveal that IQI has a detrimental impact on the spectrum sensing performance of the FD CR transceiver, which brings significant losses in the spectrum utilization.

This research project aims to expand the capability of current US Navy Automated Test Equipment (ATE) family of testers known as the Consolidated Automated Support System (CASS). Industry research is now focused on breaking the historical construct of test equipment. Advances in the field of Synthetic Instruments have opened the door to test avionics in new ways. Every year new capabilities are developed using core hardware and increasingly capable software modules to create complex waveforms. This research creates a Digital Radio Frequency Memory (DRFM) Synthetic Instrument that can be programmed to perform a wide array of low latency Radio Frequency (RF) tests. Synthetic Instruments are defined as a concatenation of hardware and software modules used in combination to emulate a traditional piece of electronic instrumentation. This Synthetic Instrument couples high speed Analog-to-Digital Converters (ADC) to high speed Digital-to-Analog Converters (DAC) with Field Programmable Gate Arrays (FPGA) in between for digital signal processing. An RF front end is used to down convert the RF to baseband where it is sampled, modified, and up converted back to RF. The FPGA performs Digital Signal Processing (DSP) on the signal to achieve the desired output. Application of this DRFM in automated testing is demonstrated using a Reconfigurable Transportable Consolidated Automated Support System (RTCASS) tester at Naval Air Systems Command (NAVAIR) Jacksonville, FL. The Unit Under Test (UUT) is an ALQ-162 Defensive Electronic Countermeasures (DECM) receiver-transmitter. Ultra-low latency signals are generated to simulate enemy jamming stimulus. As the ALQ-162 detects and responds to the input, the DRFM switches to a new frequency. The time taken by the ALQ-162 to acquire, respond, and re-acquire is measured. This test confirms the internal Yttrium Iron Garnet (YIG) oscillator meets slew specifications. Currently Navy ATE can only test RF units using high latency steady state tests. This research project developed a supplemental unit that can be added to the VXI chassis in the CASS family of testers and conduct ultra-low latency active tests. The instrument acts as hardware-in-the-loop to perform real-time tests including a new capability to measure jamming response time from DECM avionics. Demonstrated performance capabilities include: latency <; 100 ns, output Spurious-Free Dynamic Range (SFDR) > 80 dBc, input SFDR > 60 dBc, frequency tuning resolution <; 2 Hz, and frequency settling time <; 0.5 ns. New RF capabilities developed by this effort parallel similar research ongoing for digital test instruments like the Teradyne High Speed Subsystem. Incorporating this Digital RF Memory synthetic instrument into current and future ATE will improve readiness and supportability of the fleet. Improvements demonstrated by this research project will expand the type and quantity of assets able to be tested by current and future ATE.

Planar Beam-forming Antenna Array for 60-GHz Broadband Communication