A 4-channel 24–27 GHz CMOS differential phased-array receiver

An 8-elements Ku-band phased-array transmitter with built-in-self-test (BIST) capability is presented. A fully symmetrical coupler feed line is used to improve the accuracy of the BIST and calibration procedure. 5-bit phase shifters and 4-bit attenuators with less phase and amplitude errors are designed to control the beam direction and side lobes. The RMS phase and amplitude errors of the phase shifters are less than 3.6° and 0.8 dB, respectively. The RMS amplitude and phase errors of the attenuators are less than 0.94 dB and 3.2°. The measured single path power gain including the power divider is 11.9 dB. The output referred PldB is 13 dBm for each channel. ESD protection and temperature sensors are integrated. The chip is fabricated in 180 nm bulk CMOS technology. Compact design is adopted to minimize the size of each channel, which is suitable for the larze-scale phased-array system. The size of the whole chip is $\mathbf{8.5x3 mm}^{\mathbf{2}}$ , and that of each channel is $\mathbf{3.8x0.5 mm}^{\mathbf{2}}$ .

This paper presents a 60 GHz low gain imbalance low noise amplifier (LNA)-phase shifter (PS) in 65 nm CMOS for phased-array receiver. The proposed LNA-PS consists of an LNA and PS. The LNA with 1-stage current steering cascode provides 1-dB step 2-bit gain control with almost constant phase response. Thus, gain imbalance of the 4-bit PS is compensated. The LNA-PS is optimized for a phased-array receiver and the measured gain for 4-bit phase states is 16.5±2.2 dB over 57–66 GHz. The RMS gain and phase errors are < 6.3° and < 0.82 dB over 57–66 GHz, respectively. The chip consumes 13 mW from 1 V power supply. The core chip size is 0.3 mm2.

We present an ultra-low-power SiGe BiCMOS receiver front-end for X-band phased-array radar systems. The receiver, which consists of two LNAs and a 3-bit phase shifter, consumes only 4 mW of dc power while achieving over 10 dB of gain, less than 5 dB noise figure, and an OTOI of over 10 dBm. In addition, the RMS gain and phase errors were less than 0.5 dB and 2∘, respectively. This design demonstrates possible applications of SiGe HBT technology for use in ultra-low-power radar systems.

In a shot-noise-limited (coherent state) phasesensing interferometer, the root-mean-square (rms) phase error is ~ 1 / N av 1 / 2 where Nav is the average number of detected photons. In an optimized squeezed-state interferometer, the rms phase error goes as 1/Nav. We have considered the phase measurement problem from the viewpoint of quantum estimation theory.1 In particular, for the problem of optimum phase-shift estimation from observation of a single mode of the radiation field under an average photon number constraint, we have found both the optimum quantum state and the optimum quantum measurement. The former turns out to have a truncated number-state expansion whose coefficients, out to the truncation point, fall off as 1/n. The latter turns out to be the Susskind-Glogower phase operator. More important, the resulting phase estimation performance improves as 1 / N av 2 .

A 28-GHz eight-element phased-array receiver front-end with compact size in 65-nm CMOS technology for 5G new radio

This paper presents a 6-bit bidirectional variable-gain vector-summing active phase shifter (BVG-AVSPS) in TSMC 65nm CMOS technology. The proposed BVG-AVSPS consists of a novel bidirectional quadrature generator, four dual-function bidirectional amplifiers and two input/output matching networks. The proposed hybrid-based quadrature generator achieves low orthogonal amplitude and phase mismatches over a wideband with bidirectionality. Dual-function bidirectional amplifiers are employed to achieve either vector modulation or gain control functions in different operational directions. To improve the phase shifting accuracy during gain tuning, compensation transistors are employed in the dual-function bidirectional amplifiers to minimize additional phase variation. The proposed input/output networks based on L-type coupled inductors ensure proper impedance matching for both input and output in TX and RX modes. For both TX and RX modes over 24 GHz~32 GHz, the measured RMS phase and gain errors are 1.25<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∘</sup>~2.4<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∘</sup> and 0.42 dB~0.56 dB throughout 12.3 dB gain tuning range, respectively. With the help of the compensation transistors, measured phase variation is less than ±2.1<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∘</sup> during output gain tuning. The core area of proposed BVG-AVSPS is 625 µm×355 µm.

This paper presents a 77–101 GHz active 6-bit phase shifter based on a vector-modulated technique in 65 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$n$</tex> m SOI CMOS technology for W-band phased-array systems. Optimizations of the impedance-invariant variable gain amplifier (VGA) are performed to reduce the phase error and gain error among the phase states. In addition, a quadrature signal generator composed of a 90-degree hybrid and a pair of Marchand balun is exploited for wideband applications. The proposed phase shifter achieves 5.6° phase step, < 2.0° RMS phase error and < 0.8dB RMS gain error over 77–101 GHz. The total power consumption is 31mW and the core area of the phase shifter is only 0.2mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

An X-band core chip is designed and fabricated in 0.18- CMOS technology, which can significantly reduce the monolithic microwave integrated circuit count required for realizing an active beam-former T/R module. The core chip consists of two RX/TX paths, each of which includes a 6-b phase shifter, a 6-b attenuator, along with two input and output amplifiers. A new architecture for realizing such a core chip system and a low loss circuit for 5.625° phase shift block are proposed. The overall rms phase and gain errors are better than 2° and 0.25 dB, respectively, in both RX/TX paths. The gain of each path is around 12 dB, while the output 1-dB compression point is higher than 10 dBm over the band of interest.

Until now, four different types of first‐order digital phase‐locked loop (DPLL) for tracking of clock signal have been reported which are distinguished mainly by a difference in the control circuit. The performance of these digital loops is determined by rms phase error and transient response which are obtained in the reporter's own way established on a basis of Markov theory. However, performance comparison has not yet been made.In this paper, first, it is proved that phase error sequences of four digital loops are all classified into semi‐Markov sequences (SMS) if time jitter in each cycle of the input signal is an independent random variable with a certain distribution function.Second, under the condition that time jitter is an independent random variable with Gaussian distribution, the rms phase error and power density spectrum of the phase error sequence are computed for typical values of input variance according to formulas derived for SMS.Finally, using this curve and equivalent first‐order linear PLL, the rms phase error, loop noise bandwidth and phase amplification factor are obtained; and based on these results, the performance of four digital loops is discussed.

This letter demonstrates a Ka-band 4-beam phased-array receiver in 65-nm CMOS. To generate four balanced beams from two inputs, a passive 4-beam symmetrical differential network is employed to achieve balanced signal distribution. With the use of passive vector-modulated phase shifter and switched-type attenuator, the receiver consumes a current of only 40 mA under 1-V supply voltage. The 4-beam receiver shows 3-dB gain per channel. From 27 to 31 GHz, the RMS gain error and phase error are .0.4 dB and .4°, respectively. Beam-to-beam couplings are investigated, and the measured beam-to-beam isolation is better than -32 dB from 27 to 31 GHz. The chip size is 2.6 × 4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with pads included. To author's knowledge, this letter reports the first CMOS phased-array receiver with four balanced beams.

This paper presents a complete 8-element X/Ku-band phased array based on a single silicon chip. The phased array is integrated together with the antennas and digital control circuitry on a single Teflon board. The chip-on-board package, together with 8 X/Ku-band RF inputs and one RF output in a 2.2×2.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area, and the appropriate grounding and Vcc connections, are modeled using a 3-D EM solver. The design results in a low coupling between the different RF ports, and ensures stability even with a channel gain of 20 dB at 12 GHz. The measured patterns show a near-ideal performance up to a scan angle of 60° with an instantaneous scanning bandwidth of 11.4-12.6 GHz (limited by non true-time delay connections between the antennas and the chip). Temperature tests indicate that the silicon chip maintains excellent phase stability and rms phase error up to 100°C. To our knowledge, this represents the first system-level measurements on silicon-chip phased arrays.

A frequency divider providing quadrature outputs up to 30GHz is presented. Rms phase error and rms clock jitter are discussed in the context of OFDM systems, where the usual phase error correction in the digital baseband processor is included. A measurement technique for the static phase error between the in-phase and quadrature signal is proposed using an integrated single-sideband mixer in conjunction with an integrated 1:256 frequency divider. For a 20GHz I/Q output signal a static phase error of 0.16° is obtained from these measurements. The quadrature divider core draws 35mA from a 3.3 V supply and occupies 0.2 mm2 chip area, including output buffers and two differential delay lines for I/Q adjustment.

This paper demonstrates a Ka-band CMOS phased-array receiver capable of generating four balanced beams from two inputs. A passive four-beam symmetrical differential network is proposed to distribute two input signals to eight channels and facilitate beam generation at the outputs in the receiver. The detailed design and optimization of the passive four-beam differential network are presented. Using a 6-bit passive vector-modulated phase shifter and a 5-bit switched-type attenuator in each channel, we implement a phase control of 360° with<; 4° RMS phase error and a gain control of 17 dB with <; 0.35 dB RMS gain error from 27 to 31 GHz. The receiver consumes a current of only 40 mA under 1 V supply voltage. Eight channels of the four-beam phased-array receiver were measured and a gain mismatch of less than 0.3 dB has been achieved. Beam to beam couplings are investigated by measurements and beam-to-beam isolation are better than 32 dB from 27 to 31 GHz. The chip size is 2.6×4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> including all digital control circuitry and pads.

A four-element phased-array front-end receiver based on 4-bit RF phase shifters is demonstrated in a standard 0.18-mum SiGe BiCMOS technology for <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i> -band (30-50 GHz) satellite communications and radar applications. The phased-array receiver uses a corporate-feed approach with on-chip Wilkinson power combiners, and shows a power gain of 10.4 dB with an IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> of -13.8 dBm per element at 38.5 GHz and a 3-dB gain bandwidth of 32.8-44 GHz. The rms gain and phase errors are les1.2 dB and les8.7deg for all 4-bit phase states at 30-50 GHz. The beamformer also results in les0.4 dB of rms gain mismatch and les2deg of rms phase mismatch between the four channels. The channel-to-channel isolation is better than -35 dB at 30-50 GHz. The chip consumes 118 mA from a 5-V supply voltage and overall chip size is 1.4times1.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> including all pads and CMOS control electronics.

This article presents a low-power, high-gain, high-linearity phased-array transmit (Tx) beamformer chip in a 45-nm RFSOI process. An architecture employing a power amplifier with neutralization, a 180° active phase shifter and 11/22/45/90° passive phase shifter result in high linearity and low power consumption. The measured gain is 22 dB with a 3-dB bandwidth of 57.5–65.5 GHz and an ${\mathrm{ OP}}_{1\,{\mathrm{ dB}}}$ and ${\mathrm{ OP}}_{\mathrm{ sat}}$ of 7.5–10 dBm and 9.5–11.5 dBm at 57–64 GHz, respectively. A peak power-added efficiency (PAE) of 14.6% and 17.6% at 60 GHz is achieved at $P_{1\,{\mathrm{ dB}}}$ and $P_{\mathrm{ sat}}$ , respectively. The measured rms phase and gain errors are $ and ${\mathrm{ OP}}_{1\,{\mathrm{ dB}}}$ . Complex modulation measurements using a 400 MBaud 64-QAM waveform show an error vector magnitude (EVM) of 5% (−26 dB) at an average power of 5 dBm and with a dc power consumption of only 52 mW, resulting in a linear PAE of 6.1%. Also, 18–20 Gbps data rates are demonstrated with an EVM < 5% (64-QAM) and < 9% (16-QAM) at 60 GHz. To the author’s knowledge, this work achieves state-of-the-art linearity and efficiency for 60-GHz communication systems.