A Ka-Band CMOS 4-Beam Phased-Array Receiver With Symmetrical Beam-Distribution Network

This paper demonstrates a Ka-band CMOS phased-array receiver capable of generating four balanced beams from two inputs. A passive four-beam symmetrical differential network is proposed to distribute two input signals to eight channels and facilitate beam generation at the outputs in the receiver. The detailed design and optimization of the passive four-beam differential network are presented. Using a 6-bit passive vector-modulated phase shifter and a 5-bit switched-type attenuator in each channel, we implement a phase control of 360° with<; 4° RMS phase error and a gain control of 17 dB with <; 0.35 dB RMS gain error from 27 to 31 GHz. The receiver consumes a current of only 40 mA under 1 V supply voltage. Eight channels of the four-beam phased-array receiver were measured and a gain mismatch of less than 0.3 dB has been achieved. Beam to beam couplings are investigated by measurements and beam-to-beam isolation are better than 32 dB from 27 to 31 GHz. The chip size is 2.6×4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> including all digital control circuitry and pads.

A four-element phased-array front-end receiver based on 4-bit RF phase shifters is demonstrated in a standard 0.18-mum SiGe BiCMOS technology for <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i> -band (30-50 GHz) satellite communications and radar applications. The phased-array receiver uses a corporate-feed approach with on-chip Wilkinson power combiners, and shows a power gain of 10.4 dB with an IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> of -13.8 dBm per element at 38.5 GHz and a 3-dB gain bandwidth of 32.8-44 GHz. The rms gain and phase errors are les1.2 dB and les8.7deg for all 4-bit phase states at 30-50 GHz. The beamformer also results in les0.4 dB of rms gain mismatch and les2deg of rms phase mismatch between the four channels. The channel-to-channel isolation is better than -35 dB at 30-50 GHz. The chip consumes 118 mA from a 5-V supply voltage and overall chip size is 1.4times1.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> including all pads and CMOS control electronics.

An 8-elements Ku-band phased-array transmitter with built-in-self-test (BIST) capability is presented. A fully symmetrical coupler feed line is used to improve the accuracy of the BIST and calibration procedure. 5-bit phase shifters and 4-bit attenuators with less phase and amplitude errors are designed to control the beam direction and side lobes. The RMS phase and amplitude errors of the phase shifters are less than 3.6° and 0.8 dB, respectively. The RMS amplitude and phase errors of the attenuators are less than 0.94 dB and 3.2°. The measured single path power gain including the power divider is 11.9 dB. The output referred PldB is 13 dBm for each channel. ESD protection and temperature sensors are integrated. The chip is fabricated in 180 nm bulk CMOS technology. Compact design is adopted to minimize the size of each channel, which is suitable for the larze-scale phased-array system. The size of the whole chip is $\mathbf{8.5x3 mm}^{\mathbf{2}}$ , and that of each channel is $\mathbf{3.8x0.5 mm}^{\mathbf{2}}$ .

A 5-bit 360° active phase shifter of digital control with a novel two-step vector-sum technique in 0.18μm SiGe process is presented in this brief for X-band phased arrays. The two-step vector-sum technique is based on a sub-phase shifter array controlled by high quality logic circuit to avoid the issue of control circuit with low accuracy in the conventional scheme. The implemented phase shifter features good performance of 11.25° phase resolution and full 360° phase synthesizing between 8-12 GHz. Measurements display that the RMS gain error is below 0.6 dB while the RMS phase error is lower than 4.6°. The measured insertion loss is less than - 11.9 dB at 12 GHz while the return loss is better than - 13 dB over 8 to 12 GHz. With a 3.3V voltage supply, the DC power consumption is 73.92 mW. The designed phase shifter has a compact size of 0.6 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

This paper presents a 60-GHz low-loss compact 4-b phase shifter in a 65-nm CMOS. It is based on a 1-b high-pass/low-pass structure and a 3-b switched-filter structure, and employs fully custom-designed capacitors with a high quality factor for low insertion loss. The phase shifter with custom-designed capacitors reduces an insertion loss by 2.6 dB at 60 GHz. The average insertion loss is 8.1 dB at 60 GHz, and the return loss is better than 10.6 dB over a range of 57-66 GHz. The measured 16-output state of the fabricated phase shifter has a phase resolution of 22.5° with an rms phase error less than 5.5° over the 57-66 GHz range. The fabricated phase shifter has a compact core size of 0.42 mm × 0.22 mm. To the best of our knowledge, this phase shifter achieves the lowest insertion loss and the smallest core area of all the published 60-GHz 360° -coverage passive CMOS phase shifters.

In a shot-noise-limited (coherent state) phasesensing interferometer, the root-mean-square (rms) phase error is ~ 1 / N av 1 / 2 where Nav is the average number of detected photons. In an optimized squeezed-state interferometer, the rms phase error goes as 1/Nav. We have considered the phase measurement problem from the viewpoint of quantum estimation theory.1 In particular, for the problem of optimum phase-shift estimation from observation of a single mode of the radiation field under an average photon number constraint, we have found both the optimum quantum state and the optimum quantum measurement. The former turns out to have a truncated number-state expansion whose coefficients, out to the truncation point, fall off as 1/n. The latter turns out to be the Susskind-Glogower phase operator. More important, the resulting phase estimation performance improves as 1 / N av 2 .

This paper presents a 24.25–26.65 GHz 6-bit phase shifter in 65nm CMOS technology. The proposed architecture of the phase shifter divides the 6-bit phase shifter into one 3-bit and three 1-bit sub phase shifters. The low resolution sub phase shifters can be implemented just by switches and sub VGA cells which can lower the phase error apparently. The phase shifter results in a simulated RMS phase error <1.7°, meeting the requirement of 6-bit phase shifter. And the RMS gain error is less than 1.27dB in entire frequency range. The total consumption is 58mW and the core chip size is 1.15×0.85 mm2.

This brief presents a low-noise K-band phased array receive channel implemented in a 130-nm SiGe BiCMOS process. The IC consists of a cascode LNA, a vector modulator phase shifter (PS), and a current-steering VGA. The LNA employs a shunt inductor at the intermediate node of the cascode for noise reduction purposes. The PS generates I/Q signals by lumped quadrature hybrids for low noise operation. Various process compensation capabilities are employed within the PS to reliably achieve high resolution. The measured results demonstrated a peak gain of 28.5 dB at 24 GHz with a 3-dB bandwidth of 22–27 GHz. The measured noise figure is 3.3 dB, which is better than state-of-the-art among Si-based phased-array channels. For 6-b phase control, the rms phase error is 4° and 0.2° without and with calibration, respectively; the rms gain error being 1 dB for both cases. For 4-b gain control with 0.4-dB/step, the rms amplitude/phase errors are 0.1-dB/0.5°. Across different phase settings, the IC has an OP1dB of −2 to −3 dBm, with a power consumption of 48 mW. The total chip area is 1.33 mm2, excluding the pads.

The paper presents a 24–27 GHz 4-channel CMOS differential phased array receiver front-end with integrated baluns, ESD protection and VGAs. The differential implementation of the phased array significantly reduces the substrate coupling effects. The measured array performance shows an input and output match of ≪ −10 dB, 12–15 dB gain, 7.8–9.5 dB NF, an IIP3 of −9 to −12 dBm, an input P 1dB of −19 to −22 dBm, and a 4-bit phase control with an rms gain and phase errors of ≪ 0.35 dB and ≪ 6°, respectively, all at 24–27 GHz. The measured rms gain and phase errors due to on-chip coupling effects are ≪ 0.25 dB and ≪ 2° at 20–30 GHz. The chip consumes 155 mA from a 1.5 V supply with an area of 4 mm2 and can operate over a 3 GHz instantaneous bandwidth (limited by the gain response).

Until now, four different types of first‐order digital phase‐locked loop (DPLL) for tracking of clock signal have been reported which are distinguished mainly by a difference in the control circuit. The performance of these digital loops is determined by rms phase error and transient response which are obtained in the reporter's own way established on a basis of Markov theory. However, performance comparison has not yet been made.In this paper, first, it is proved that phase error sequences of four digital loops are all classified into semi‐Markov sequences (SMS) if time jitter in each cycle of the input signal is an independent random variable with a certain distribution function.Second, under the condition that time jitter is an independent random variable with Gaussian distribution, the rms phase error and power density spectrum of the phase error sequence are computed for typical values of input variance according to formulas derived for SMS.Finally, using this curve and equivalent first‐order linear PLL, the rms phase error, loop noise bandwidth and phase amplification factor are obtained; and based on these results, the performance of four digital loops is discussed.

This paper presents a 60 GHz low gain imbalance low noise amplifier (LNA)-phase shifter (PS) in 65 nm CMOS for phased-array receiver. The proposed LNA-PS consists of an LNA and PS. The LNA with 1-stage current steering cascode provides 1-dB step 2-bit gain control with almost constant phase response. Thus, gain imbalance of the 4-bit PS is compensated. The LNA-PS is optimized for a phased-array receiver and the measured gain for 4-bit phase states is 16.5±2.2 dB over 57–66 GHz. The RMS gain and phase errors are < 6.3° and < 0.82 dB over 57–66 GHz, respectively. The chip consumes 13 mW from 1 V power supply. The core chip size is 0.3 mm2.

This letter presents a three-stage 60-GHz phase-invariant variable gain low-noise amplifier (VG-LNA) with accurate gain tuning step and large gain tuning range. A single-ended cascode amplifier is adopted as the first stage to integrate the transmit/receive (T/R) switch and achieve wideband input matching. Besides, with gain interpolation techniques, by combining three different gain cells, a stacked gain-boosting variable gain amplifier is proposed to realize wide-range and accurate dB-linear gain tuning functions simultaneously, showing the merits of low layout and logic control complexity. Fabricated in a 65-nm CMOS process, the VG-LNA consumes 38.4 mW with a core area of 0.08 mm2. With measurements, the proposed VG-LNA achieves a peak gain of 20 dB with a 3-dB bandwidth over 53–66.5 GHz and a minimum noise figure (NF) of 6.3 dB. Across a 17.5-dB gain tuning range, it realizes an average gain resolution of 0.47 dB, with an rms phase and amplitude error of less than 2.6° and 0.14 dB, respectively.

Design and measured results of X band 6-bit digital phase shifter MMIC is presented in this paper. This phase shifter is designed in the frequency range of 8.5-10.5GHz with phase resolution of 5.6&#x00B0; The design is based on a GaAs Enhancement/Depletion Process. Topology architectures for the design of the individual phase bits are derived to maintain low insertion loss, flat phase response and small MMIC die size. TTL driver circuit is embedded in the design to control the phase shift with TTL control inputs. It works on +5V,-5V Supply voltages. The measured results of digital phase shifter are 6dB insertion loss, 3&#x00B0; RMS phase Error, Peak phase Error of &#x00B1;10&#x00B0; and RMS amplitude error of 0.4dB across the all 64 phase states.

A 60-GHz vector summing phase shifter has been implemented in 90-nm CMOS. Using digital tunable current-splitting technique with π-type LPF and T-type HPF, a quadrature adjustable amplitude generator is developed to improve insertion loss and adjust quadrature signals' amplitudes. It has a high Q-factor passive I/Q signal network with wide phase range. In addition, a balun based current-reuse technique is applied to further reduce power consumption. The total consumed DC current is 11 mA under 1.8 V VDD. At 60 GHz, the phase shifter with an output balun (with loss of 1.6 dB) achieves tested gain of −0.4∼2.5 dB. From 57 to 64 GHz, The measured RMS gain error and RMS phase error with phase calibration are 0.75∼1.6 dB and 2.3°∼7.6°, respectively.

In this letter, a highly compact, bidirectional, wideband 6-bit resolution passive phase shifter (PS) is presented in low-cost 130-nm CMOS technology. A compact Lange differential hybrid is designed in this letter to provide quadrature signals from the input. The compact Lange hybrid is followed by a switching matrix that generates weighted sums of the quadrature signals to cover 360° and additional controlled loss using single pole single throw (SPST) switches. The matrix consists of 12 transistors, each of which is controlled by a three-level gate voltage (0, 0.6, and 1.2 V) providing higher resolution in phase shifts. The chip achieves the state-of-the-art performance with 10-dB insertion loss across 28–38 GHz. The chip also achieves an rms gain error of 0.6 dB and an rms phase error of 3° in the bandwidth, consuming no dc power and only 0.15 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> including baluns.