Comparative study on dpll's based on power density spectrum of phase error sequences

The limitations and the effect of the performance of the binary phase detector on the overall performance of the digital phase-locked loop is the main focus of the research presented in this proposal. In the first part of the research, the gain limitation of the binary phase detector on the performance of the digital Bang-Bang phase-locked loop is investigated. Then to validate the concept that is explained and to improve the performance of the digital loop under the gain limitation, two schemes are explored and explained. In one scheme a random bit-stream which is noise-shaped using a software defined modulator is used to dither the reference and improve the performance and in the second scheme a Time-Amplifier is used to improve the digital loop performance by preventing the phase detector from operating in metastable region.

In a shot-noise-limited (coherent state) phasesensing interferometer, the root-mean-square (rms) phase error is ~ 1 / N av 1 / 2 where Nav is the average number of detected photons. In an optimized squeezed-state interferometer, the rms phase error goes as 1/Nav. We have considered the phase measurement problem from the viewpoint of quantum estimation theory.1 In particular, for the problem of optimum phase-shift estimation from observation of a single mode of the radiation field under an average photon number constraint, we have found both the optimum quantum state and the optimum quantum measurement. The former turns out to have a truncated number-state expansion whose coefficients, out to the truncation point, fall off as 1/n. The latter turns out to be the Susskind-Glogower phase operator. More important, the resulting phase estimation performance improves as 1 / N av 2 .

An 8-elements Ku-band phased-array transmitter with built-in-self-test (BIST) capability is presented. A fully symmetrical coupler feed line is used to improve the accuracy of the BIST and calibration procedure. 5-bit phase shifters and 4-bit attenuators with less phase and amplitude errors are designed to control the beam direction and side lobes. The RMS phase and amplitude errors of the phase shifters are less than 3.6° and 0.8 dB, respectively. The RMS amplitude and phase errors of the attenuators are less than 0.94 dB and 3.2°. The measured single path power gain including the power divider is 11.9 dB. The output referred PldB is 13 dBm for each channel. ESD protection and temperature sensors are integrated. The chip is fabricated in 180 nm bulk CMOS technology. Compact design is adopted to minimize the size of each channel, which is suitable for the larze-scale phased-array system. The size of the whole chip is $\mathbf{8.5x3 mm}^{\mathbf{2}}$ , and that of each channel is $\mathbf{3.8x0.5 mm}^{\mathbf{2}}$ .

Conventional research for signal tracking of the Global Navigation Satellite System (GNSS) uses a loop filter to minimize the effect of measurement noise. Although for a few decades, research into the optimal GNSS tracking loop has been based on similarity between signal tracking and general control loop theory, it has mainly focused on optimal estimator, or shown vulnerability for high dynamic signal tracking. To enhance the performance of the optimal signal tracking loop, this paper proposes new plant modeling for optimal GNSS signal tracking that consists of both optimal estimator and controller. The proposed plant modeling is able to maximize the performance of the optimal signal tracking loop due to the relationships between code and carrier tracking, and between the frequency and phase of the carrier. In addition, the plant clearly defines a relationship between the general control loop and GNSS tracking loop, so that the plant is ready to be applied to various control theories for GNSS signal tracking. To assess the performance of the proposed plant modeling, we implement a linear quadratic Gaussian (LQG) tracking loop based on the new proposed plant and process simulation data. Comparison of the processing results to those of conventional research shows improved performance of the proposed plant modeling.

A frequency divider providing quadrature outputs up to 30GHz is presented. Rms phase error and rms clock jitter are discussed in the context of OFDM systems, where the usual phase error correction in the digital baseband processor is included. A measurement technique for the static phase error between the in-phase and quadrature signal is proposed using an integrated single-sideband mixer in conjunction with an integrated 1:256 frequency divider. For a 20GHz I/Q output signal a static phase error of 0.16° is obtained from these measurements. The quadrature divider core draws 35mA from a 3.3 V supply and occupies 0.2 mm2 chip area, including output buffers and two differential delay lines for I/Q adjustment.

A digital tanlock loop (DTL) is a nonuniform sampling digital phase-locked loop (DPLL) whose phase error detector, using the tan/sup -1/[/spl middot/] function with in-phase and quadrature samples of incoming signal, has a linear characteristic with a period of 2/spl pi/. In this paper, we study the application of an N-phase DTL in digital cellular radio with /spl pi//4-DQPSK modulation. The performance degradation due to fading effect is investigated in terms of bit error rate and steady state phase error variance by computer simulation. It is shown that, in the digital cellular radio system, the performances on both bit error rate and phase error variance using DTL are far better than that using the traditional digital N-phase I-Q loop.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The performance of carrier recovery and tracking for CDMA systems was evaluated in a realistic land mobile satellite channel as function of elevation angle and pilot channel signal-to-noise ratio. The carrier frequency is recovered by an AFC loop assuming a rough estimate of the carrier frequency is available. After frequency recovery and tracking is accomplished, the residual phase error is estimated by a feedforward structure. The performance results are presented in terms of the AFC loop acquisition time, the rms frequency error and the rms phase error. The results indicate that a two-step frequency acquisition strategy is useful to reach a good compromise between short acquisition time and low rms frequency error. The worst-case acquisition times of the AFC loop were achieved at low elevations, being below 297 ms at signal-to-noise ratios of 9 dB or higher. The worst-case frequency and phase errors were also found at low elevations, being 11.4 Hz and 23.3 degrees at 9 dB SNR, respectively.

A method for synthesizing an all digital phase-locked loop is proposed. The design is based on the digitization of a continuous system whereby the s-plane poles and zeros of a specified differential equation are mapped to the z-plane poles and zeros of a corresponding difference equation using the matched z-transform method. The critical parameters are specified and their influence on loop performance is noted. The performance of the digital loop is shown through analysis and computer simulations. >

The paper presents a 24–27 GHz 4-channel CMOS differential phased array receiver front-end with integrated baluns, ESD protection and VGAs. The differential implementation of the phased array significantly reduces the substrate coupling effects. The measured array performance shows an input and output match of ≪ −10 dB, 12–15 dB gain, 7.8–9.5 dB NF, an IIP3 of −9 to −12 dBm, an input P 1dB of −19 to −22 dBm, and a 4-bit phase control with an rms gain and phase errors of ≪ 0.35 dB and ≪ 6°, respectively, all at 24–27 GHz. The measured rms gain and phase errors due to on-chip coupling effects are ≪ 0.25 dB and ≪ 2° at 20–30 GHz. The chip consumes 155 mA from a 1.5 V supply with an area of 4 mm2 and can operate over a 3 GHz instantaneous bandwidth (limited by the gain response).

This paper presents a 77–101 GHz active 6-bit phase shifter based on a vector-modulated technique in 65 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$n$</tex> m SOI CMOS technology for W-band phased-array systems. Optimizations of the impedance-invariant variable gain amplifier (VGA) are performed to reduce the phase error and gain error among the phase states. In addition, a quadrature signal generator composed of a 90-degree hybrid and a pair of Marchand balun is exploited for wideband applications. The proposed phase shifter achieves 5.6° phase step, < 2.0° RMS phase error and < 0.8dB RMS gain error over 77–101 GHz. The total power consumption is 31mW and the core area of the phase shifter is only 0.2mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

The theoretical relation between the amplitude distribution of noise and the resulting distribution of phase error in a sinusoid is developed for all values of the parameters. It is shown that the rms phase error can be determined directly from the noise amplitude distribution. The method is illustrated using experimental samples of atmospheric noise amplitude distributions observed in a particular receiving system for VLF timing pulses. For amplitudes well above manmade interference the atmospheric noise in these samples closely follows a 2¾‐power law.

This chapter begins with a brief description of the requirements for image quality, the measurement of the wavefront aberration with a Shack–Hartmann (SH) sensor and its decomposition in a set of orthogonal functions named the Zernike modes. Next, the Kolmogorov turbulence model is used, together with the assumption of frozen turbulence shape transported by the wind to evaluate the RMS value of the phase error, the image quality, and the power spectral density of the various Zernike modes. The next section discusses the main features of deformable mirrors for adaptive optics, with a special attention to the bimorph piezoelectric mirrors in various actuator configurations (keystone and honeycomb). The following section is devoted to the feedback control using a frequency-shaped singular value decomposition (SVD) controller and assuming a quasi-static response of the deformable mirror; the closed-loop response of the various Zernike modes and the RMS phase error is evaluated as a function of the control bandwidth. Next, a dynamical model of the mirror is used and the control-structure interaction is analyzed, leading to spillover; the importance of the structural damping of the vibration modes is pointed out. The damping augmentation via passive piezo shunt and active damping using modal filtering is then analyzed. The chapter concludes with some remarks on manufacturing and a list of references.

A study on the impact of the phase errors distribution on the performances of the phased array systems has been produced using a complete and behavioral model for radiation-pattern characteristics . The study has shown how the phase errors distribution actually affects the performances demonstrating that the rms phase error is a valuable figure of merit of phased array systems but it is not sufficient to completely describe the behavior of a real system. The used model has many input parameters and it has a lot of features, such as parameter simulations with results analysis, unconventional two-dimensional color graph representation capability in order to show more clearly the results. The results of the study demonstrating the previous considerations have been reported.

Design and measured results of X band 6-bit digital phase shifter MMIC is presented in this paper. This phase shifter is designed in the frequency range of 8.5-10.5GHz with phase resolution of 5.6&#x00B0; The design is based on a GaAs Enhancement/Depletion Process. Topology architectures for the design of the individual phase bits are derived to maintain low insertion loss, flat phase response and small MMIC die size. TTL driver circuit is embedded in the design to control the phase shift with TTL control inputs. It works on +5V,-5V Supply voltages. The measured results of digital phase shifter are 6dB insertion loss, 3&#x00B0; RMS phase Error, Peak phase Error of &#x00B1;10&#x00B0; and RMS amplitude error of 0.4dB across the all 64 phase states.

This paper presents a compact 14–18 GHz 6-bit attenuator in 0.35-μm SiGe BiCMOS technology. To realize size miniaturization, large attenuation range and low insertion loss, the switched Pi/T attenuator topology is employed. It adopts serial and shunt single-pole-single-throw switches merged with a resistive network to control attenuation accurately. In addition, the proposed attenuators use a novel inductive low-pass filter for phase correction to compensate the phase error in difference states. The designed prototype achieves an attenuation range of 31.5 dB in a 0.5-dB step size with 64 states, average insertion loss of 8±0.6 dB, P1dB of better than 10 dBm, input/output return losses of better than −10/-11 dB in all states, and chip size of 0.80×0.34 mm2 only excluding testing pads. The calculated root-mean-square (rms) amplitude error is less than 0.29 dB, with rms phase error is less than 3.9o in the designed frequency range.