A Background Sample-Time Error Calibration Technique Using Random Data for Wide-Band High-Resolution Time-Interleaved ADCs

The behavior of the Analog-to-Digital converter (ADC) strongly affects the global performance of the modem communication systems in terms of metrological uncertainty. Due to errors in the manufacturing process, all ADCs in a time interleaved ADC system are not exactly identical. It means that gain and offset mismatch errors are introduced in the digital signal processing. These errors cause distortion in the sampled signal. In this paper we present a method based on T-Model neural network for compensation of the mismatch errors. The compensation can be working while the ADCs are still running. The method is also adaptive to slow changes of the errors parameters. Combining with prediction of signal based on chaotic neural network, we can reach obvious improvement for ADC system and save a large amount of calculating time. This method has been validated with simulations of a time interleaved ADC system.

High-speed ADC systems with HBTs for measuring instrument applications

The rapid development of digital technology requires higher Analog Digital Converter (ADC) sampling rates. Single-chip ADC is difficult to meet this require. The Time Interleaved ADC (TIADC) based on ADC parallel sampling can solve this problem and is therefore widely used. However, due to current hardware levels, the sampling interval of the TIADC is non-uniform and there is a time sampling error (TSE). There are currently a number of algorithms that can estimate the TSE, but must work in an environment where the frequency of the input signal is known. This paper improves an existing TSE estimation method that enables parameter estimation with unknown input signal frequencies. The proposed algorithm constructs the relationship between signal variance and TSE. In the implementation process, the TSE estimation value is inverted by statistical signal variance. Simulations show that the normalized TSE estimation error value variance is 0.01.

We report on an analog to digital converter (ADC) system with 8 bit resolution and a sam le rate of 8 GSa/s. The system is composed of 2 thick-fh hybrid substrates, each holding a silicon bipolar ADC chip and a custom CMOS memory chip. Each ADC chip contains two differential track and hold circuits and two folding and interpolating 2 GSa/s flash digitizers. The custom memory chip accepts data at 2 GSa/s on each of two input ports, and stores the data in a 256 Kbit SUM. The ADC system uses time interleaving of 4 paths to reach 8 GSa/s and combines hardware dither with software calibration techniques to achieve 7.6 effective bits at low frequencies and 5.3 effective bits at 2 GHz input. Thick-film Hybrid

High power consumption and hardware cost are the two challenges for practical massive MIMO systems. One promising solution is to employ low resolution analog to digital converter (ADC). In this paper, massive MIMO relaying systems are investigated with double resolution ADCs at base station receiver, where some antennas are connected to low resolution ADCs, while the rest of the antennas are connected to high resolution ADCs. Closed form expression for uplink spectral efficiency (SE) is derived using the maximum ratio combining receiver assuming perfect channel state information. Some asymptotic analysis is discussed to explore the effects of system parameters on SE such as; the number of receive antennas, ADC quantization bits, user transmit power and the rate of high precision ADC in double resolution ADC structure. Moreover, energy efficiency with some system parameters is studied. It is shown that the performance wastage owing to low precision ADCs can be recompensed by growing the number of receive antennas $$ \varvec{N} $$, following a logarithmic scaling law instead of increasing the transmit power at both of source and relay. The double resolution ADCs can achieve a better tradeoff between power consumption and SE when using 4 quantization bits. By using only around 30 antennas, the double resolution ADCs achieves its optimal energy efficiency for selecting system parameters.

A new data acquisition system has been developed continually as a part of the development of a new beam loss monitor (BLM) system for the J-PARC main ring. This development includes a newly designed front-end isolation amp that uses photo-couplers and a VME-based new analog-to-digital converter (ADC) system. Compared to the old amp, the new amp has a 10 times higher conversion impedance for the input current to the output voltage; this value is 1 MΩ. Moreover, the bandwidth was improved to from DC to 50 kHz, which is about two orders of magnitude greater than the previously used bandwidth. The theoretical estimations made in this study roughly agree with the frequency response obtained for the new system. The new ADC system uses an on-board field-programmable gate array chip for signal processing. By replacing the firmware of this chip, changes pertaining to future accelerator upgrade plans may be introduced into the new ADC system; in addition, the ADC system can be used in other applications. The sampling speed of the system is 1 MS/s, and it exhibits a 95 dBc spurious-free dynamic range and 16.5 effective number of bits. The obtained waveform and integrated charge data are compared with two reference levels in the ADC system. If the data exceeds the reference level, the system generates an alarm to dump the beams. By using the new data acquisition system, it was proved that the new BLM system shows a wide dynamic range of 160 dB. In this study, the details of the new data acquisition system are described.

This paper considers the problem of efficient block digital filter (BDF) design for calibrating timing-errors in a time-interleaved analog-to-digital converter (TIADC) system. The traditional calibrating filters can not achieve the throughout rate that the TIADC needs. This paper first brings the block digital filters for calibration of the timing-errors in the TIADC. The different BDF design methods were proposed due to the different number of TIADC channels. The proposed block digital filters can increase the parallelism of the computation and can greatly reduce the high clock speed that TIADC needs.

High-speed track-and-hold amplifier (THA) circuits are critical for high-speed, high-resolution data converters, particularly in emerging 100Gb/s optical communication systems. High-speed CMOS analog-to-digital converters (ADCs) have been demonstrated to 56GS/s, but the linearity tends to rapidly degrade at high frequency. The use of a high-speed THA can broaden the frequency response, improve the distortion performance, and mitigate some of the timing requirements for high-speed time-interleaved ADCs. Recent THA work has leveraged high-fmax Indium Phosphide (InP) HBTs to implement 50GS/s track-and-hold amplifiers. Nonetheless, a two-chip solution consisting of an InP THA and time-interleaved CMOS ADCs is extremely difficult to package while retaining high-speed performance.

We propose a hybrid Analog to Digital Converter (ADC) combined with the first-stage as a first-order feedforward incremental (FF I-) ADC and the second-stage as a SAR (Successive Approximation Register) ADC as high-precision and high-speed ADCs. As a result of simulation, the proposed hybrid ADC correctly converts data even if capacitance in FF path of the first-order I-ADC has 10% error.

A software-defined radio (SDR) for ultrawideband (UWB) communication systems places several stringent requirements on the analog-to-digital converter (ADC). One alternative to using a single ADC is to sample the received signal with an array of lower speed ADCs that were driven by interleaved sampling clocks; however, mismatches among the ADCs will result in signal distortion. This paper makes three important contributions to overcoming this problem: 1) analytical quantification of the impact of ADC gain, offset, and timing mismatches on the performance of a time-interleaved sampling ADC array for UWB signals; 2) demonstration of the efficacy of using a pilot-based matched-filter architecture to mitigate the impact of timing mismatches in the presence of multipath; and 3) implementation of an 8-ADC time-interleaved UWB SDR testbed that operates at an effective sampling frequency of 6.4 GHz. In addition, our findings allow for the design specification of the number of pilots required to obtain a desired system performance. The simulation and measured performance results from this paper demonstrate that ADC mismatches can be controlled to within plusmn10%, yielding acceptable levels of distortion and bit-error-rate (BER) performance on the UWB SDR testbed. Both analytical and simulation results also demonstrate the efficacy of a pilot-based matched filter in mitigating the impact of timing mismatch errors, even in the presence of multipath.

Offset, gain and time mismatch errors exist in the channels of the time-interleaved analog-to-digital converter (TIADC), which severely affect the signal-to-noise and distortion ratio (SNDR), spurious-free dynamic range (SFDR) and effective number of bits (ENOB). Here, an error detection and correction method of TIADC based on genetic algorithm (GA) optimization is presented. The algorithm based on sine fitting is used for the first estimation and rough correction of the input signal, and GA is used for the second detection and fine correction of channel mismatch errors on the signal after frequency domain filtering. Experimental results show that the SNDR of the TIADC system is enhanced to 92.24 dB, the SFDR is enhanced to 102.05 dB, the ENOB is enhanced to 15.03 bits and the spectrum spurs are reduced. This method provides a new idea for error detection and correction of high-resolution TIADC systems with more than 16 bits.

We have designed single-bit comparators and multi-bit flash analog-to-digital converters (ADCs) using three flavors of periodic comparators; one flavor uses a differential “quasi-one-junction” SQUID (DQOS) comparator, the second use a differential SQUID wheel comparator (DSW) and the third uses a symmetric differential SQUID wheel comparator (SDSW) with time-interleaved clocks. We have also developed a new performance analysis scheme that enables full reconstruction of input signal using a single-bit comparator. The signal is reconstructed based on multiple beat frequency measurements that track the position of the comparator thresholds in response to a dc offset to the input signal. In addition, to eliminate the frequency dependent distortions resulting from impedance mismatches over wide bandwidths, the signal and clock distribution network have been optimized using EM simulations. For distributing the clock signal to the multi-bit comparators, a 50 Ω coplanar transmission line has been designed. Test results for a 1-bit DSW comparator demonstrates a performance of 4.5 bits of resolution in Gray code for a beat frequency test using a 20 GHz input signal and 5.3 bits for 10 GHz input. 4 and 8-bit versions of the flash ADC with a DQOS comparator and a 3-bit time-interleaved ADC using the SDSW comparator have also been designed. The DQOS ADC has been tested up to 25 GHz input signal frequency with performance of 4.3 bits of resolution in Gray code for 19.7 GHz input signal. The time-interleaved ADC performance is 4.3 bits for a 15 GHz beat frequency test with an effective sampling rate of 30 GHz.

This paper presents a background timing skew calibration technique for time-interleaved analog-to-digital converters(ADCs). The timing skew between two adjacent sub- ADCs is detected in the digital domain through slope-based and statistics-based technique. Based on the detection error, the digitally controlled delay line(DCDL) is driven to minimum the timing skew. Using the proposed calibration algorithm in a 14- bit 500MS/s TI ADC model, the MATLAB simulation result shows a convergence time of 346ms under Nyquist frequency input with 1% oTs initial timing mismatch, and the proposed method can effectively reduce hardware consumption in circuit implementation.

Due to the large swath of available bandwidth, millimeter wave (mmWave) spectrum is potentially suitable to meet enhanced network capacity requirements of future generation communication systems. However, the high Analog to Digital Converter (ADC) sampling rate required to process wide band signals in the mmWave regime results in significant power consumption in the receiver hardware. In this work, an Orthogonal Frequency Division Multiplexing (OFDM) based subsampling architecture is proposed to achieve power efficient receiver design. Subbanding in association with orthogonal spreading codes using subsampling technique reduces the high sampling rate requirement of the receiver. Power consumption in the receiver is further reduced by utilizing low resolution ADC with minimal degradation in Bit Error Rate (BER) performance. In addition to this, OFDM transmission with reduced number of Fast Fourier transform (FFT) points alleviates the multi-path effects significantly, and improves the spectral efficiency. The combined effect of ADC bit resolution and subsampling on the system error performance and power consumption is studied.

This brief proposes an analog-to-digital converter (ADC) based on Generalized Sampling Theorem and derives a closed form expression of its performance, viz., signal-to-quantization noise ratio (SQNR) and alias-suppression (AS). The ADCs in the 2-channels sample the signal and its filtered version, respectively, at half the Nyquist rate. The outputs of the two ADCs are upsampled by a factor of 2, passed through appropriate reconstruction filters, and then added to give an effective sample-rate which is double that of the sample-rate of each channel ADC. Performance of the proposed ADC has been summarized for simple filters like differentiator, integrator, passive RC low-pass filter, and passive CR high-pass filters. The proposed ADC could therefore be used as an alternative to other popular ADC structures like time-interleaved, frequency-interleaved, and filter-bank ADCs, to achieve high sample-rate with minimal analog circuit overhead.