Compensation of Converter System Based on Neural Network

Sample-time error among the channels of a time-interleaved analog-to-digital converter (ADC) is the main reason for significant degradation of the effective resolution of the high-speed time-interleaved ADC. A calibration technique for sample-time mismatches has been proposed and implemented at a low level of complexity. The calibration method uses random data and is especially suitable for ADCs used in digital data communication systems. An 800-MS/s four-channel, time-interleaved ADC system has been implemented to evaluate the performance of the technique. The experimental results show that the spurious-free dynamic range of the ADC system is improved to 58.1 dB at 350 MHz. The ADC system achieves a signal-to-noise and distortion ratio of 59.6 dB at 5 MHz and 50.1 dB at 350 MHz after calibration.

High-speed ADC systems with HBTs for measuring instrument applications

We report on an analog to digital converter (ADC) system with 8 bit resolution and a sam le rate of 8 GSa/s. The system is composed of 2 thick-fh hybrid substrates, each holding a silicon bipolar ADC chip and a custom CMOS memory chip. Each ADC chip contains two differential track and hold circuits and two folding and interpolating 2 GSa/s flash digitizers. The custom memory chip accepts data at 2 GSa/s on each of two input ports, and stores the data in a 256 Kbit SUM. The ADC system uses time interleaving of 4 paths to reach 8 GSa/s and combines hardware dither with software calibration techniques to achieve 7.6 effective bits at low frequencies and 5.3 effective bits at 2 GHz input. Thick-film Hybrid

A low power fuzzy logic based variable resolution ADC for wireless ECG monitoring systems

A time-interleaved ADC system is an effective way to implement a high-sampling-rate ADC with relatively slow circuits. In the system, several channel ADCs operate at interleaved sampling times as if they were effectively a single ADC operating at a much higher sampling rate. However, mismatches such as offset, gain mismatches among channel ADCs as well as timing skew of the clocks distributed to them degrade S/N of the ADC system as a whole. This paper analyzes the channel mismatch effects in the time-interleaved ADC system. Previous analysis showed the effect for each mismatch individually, however in this paper we derive explicit formula for the mismatch effects when all of offset, gain and timing mismatches exist together. We have clarified that the gain and timing mismatch effects interact each other but the offset mismatch effect is independent from them, and this can be seen clearly in frequency domain. We also discuss the bandwidth mismatch effect. The derived formula can be used for calibration algorithms to compensate for the channel mismatch effects.

Offset, gain and time mismatch errors exist in the channels of the time-interleaved analog-to-digital converter (TIADC), which severely affect the signal-to-noise and distortion ratio (SNDR), spurious-free dynamic range (SFDR) and effective number of bits (ENOB). Here, an error detection and correction method of TIADC based on genetic algorithm (GA) optimization is presented. The algorithm based on sine fitting is used for the first estimation and rough correction of the input signal, and GA is used for the second detection and fine correction of channel mismatch errors on the signal after frequency domain filtering. Experimental results show that the SNDR of the TIADC system is enhanced to 92.24 dB, the SFDR is enhanced to 102.05 dB, the ENOB is enhanced to 15.03 bits and the spectrum spurs are reduced. This method provides a new idea for error detection and correction of high-resolution TIADC systems with more than 16 bits.

Nowadays the need for dealing with ultra-high speed Analog to Digital Converter (ADC) is becoming more and more common, from Telecommunications to Precise Instrumentation, every application is increasing the analog to digital interface data rate. The ultra-high sampling rate of the ADCs demands the use of advanced acquisition techniques as well as the latest technology available. The utilization of dedicated Application Specific Integrated Circuit (ASIC) is an expensive solution to deal with the very high throughput from the ADC and its lack of flexibility is a huge drawback. On the other hand, the technology, the architecture and the state-of-the art of the current Field Programmable Gate Arrays (FPGAs) make them especially suitable to act as interface between an ultra-high speed ADC and a data processing unit. Another extra advantage is the reconfigurability of the FPGAs, they can be quickly adapted to different ADCs or different data processing units. The purpose of this paper is to present a practical approach to interface an ultra-high speed 8-bit ADC, MAX104, from Maxim Integrated Circuit, which performs digitalization of the input signal with a sampling rate of 1Gsps and a commercial and popular FPGA, the Virtex2 Pro, from Xilinx Corporation. Once the ADC digital data have been acquired, then they can be processed by either the dedicated FPGA Digital Signal Processing (DSP) blocks, or the FPGA embedded processors or just send the data out to a PC for later processing. Hence, the proposed method of implementation can be used as front-end of a wide range of applications.

A new data acquisition system has been developed continually as a part of the development of a new beam loss monitor (BLM) system for the J-PARC main ring. This development includes a newly designed front-end isolation amp that uses photo-couplers and a VME-based new analog-to-digital converter (ADC) system. Compared to the old amp, the new amp has a 10 times higher conversion impedance for the input current to the output voltage; this value is 1 MΩ. Moreover, the bandwidth was improved to from DC to 50 kHz, which is about two orders of magnitude greater than the previously used bandwidth. The theoretical estimations made in this study roughly agree with the frequency response obtained for the new system. The new ADC system uses an on-board field-programmable gate array chip for signal processing. By replacing the firmware of this chip, changes pertaining to future accelerator upgrade plans may be introduced into the new ADC system; in addition, the ADC system can be used in other applications. The sampling speed of the system is 1 MS/s, and it exhibits a 95 dBc spurious-free dynamic range and 16.5 effective number of bits. The obtained waveform and integrated charge data are compared with two reference levels in the ADC system. If the data exceeds the reference level, the system generates an alarm to dump the beams. By using the new data acquisition system, it was proved that the new BLM system shows a wide dynamic range of 160 dB. In this study, the details of the new data acquisition system are described.

Digital signal processing (DSP) has been widely applied in optical communication systems to mitigate various signal distortions and has become one of the key technologies that have sustained data traffic growth over the past decade. However, the strict energy budget of application-specific integrated circuit-based DSP chips has prevented the deployment of some powerful but computationally costly DSP algorithms in real applications. As a result, fiber nonlinearity-induced signal distortions impede fiber communication systems, especially in wavelength-division multiplexed (WDM) transmission systems. To solve these challenges in DSP, there has been a surge of interest in implementing neural networks-based signal processing using photonics hardware (i.e., photonic neural networks). Photonic neural networks promise to break performance limitations in electronics and gain advantages in bandwidth, latency, and power consumption in solving intellectual tasks that are unreachable by conventional digital electronic platforms. This work proposes a photonic recurrent neural network (RNN) capable of simultaneously resolving dispersion and both intra and inter-channel fiber nonlinearities in multiple WDM channels in the photonic domain, for the first time to our best knowledge. Furthermore, our photonic RNN can directly process optical WDM signals in the photonic domain, avoiding prohibitive energy consumption and speed overhead in analog to digital converters (ADCs). Our proposed photonic RNN is fully compatible with mature silicon photonic fabrications. We demonstrate in simulation that our photonic RNN can process multiple WDM channels simultaneously and achieve a reduced bit error rate compared to typical DSP algorithms for all WDM channels in a pulse-amplitude modulation 4-level (PAM4) transmission system, thanks to its unique capability to address inter-channel fiber nonlinearities. In addition to signal quality performance, the proposed system also promises to significantly reduce the power consumption and the latency compared to the state-of-the-art DSP chips, according to our power and latency analysis.

A low power 10-bit 250-k sample per second (KSPS) cyclic analog to digital converter (ADC) is presented. The ADC's offset errors are successfully cancelled out through the proper choice of a capacitor switching sequence. The improved redundant signed digit algorithm used in the ADC can tolerate high levels of the comparator's offset errors and switched capacitor mismatch errors. With this structure, it has the advantages of simple circuit configuration, small chip area and low power dissipation. The cyclic ADC manufactured with the Chartered 0.35 μm 2P4M process shows a 58.5 dB signal to noise and distortion ratio and a 9.4 bit effective number of bits at a 250 KSPS sample rate. It dissipates 0.72 mW with a 3.3 V power supply and occupies dimensions of 0.42 × 0.68 mm2.

A system has been constructed and used for on-line acquisition of data at the Iowa State Synchrotron Laboratory. The principal components include eight Victoreen analog to digital converters (ADC) and a fast general purpose digital computer (SDS 910) along with the necessary interface circuitry to couple to the digitized outputs of scalers, clocks, etc. Although quite flexible in application, the ADC-to-computer interface was designed especially for efficient use (minimum deadtime and bias) both with an accelerator having a beam burst of about 100 microseconds duration and for continuous operation. To minimize ADC deadtime ineither circumstance, each 8Mc/sec ADC, equipped with an analog buffer, is connected through a plugboard to a digital buffer register synchronized to the ADC. This permits readout of the digitized pulse heights in less than one microsecond. In experiments where the ADC's operate completely independently of one another, a hardware option is provided to interpret the buffer register contents as addresses in the computer memory. This option eliminates the necessity for software programming of data input: the contents of the associated word in memory may be either incremented or decremented automatically in a minimum of two computer cycles. Some biasing in efficiency normally occurs in multiple ADC systems at high counting rates when two or more registers are waiting for readout. To reduce such bias to a negligible amount, logic governing data transfer to the computer sequences through a hierarchy of register preferences with a periodicity of 128 microseconds.

Maintaining the accuracy of a sensor system across various operating conditions has always been a challenge, especially for those operating in harsh surroundings such as a radiation environment. Concerning frequency-based sensor interfaces, supply voltage drifts and gain shift of the voltage-to-frequency converter (VFC) are critical design issues. These manifest as gain, offset, and linearity errors at the system level and therefore require continuous correction mechanisms. In this paper, dynamic gain and offset error-compensated open-loop frequency-based sensor interface architectures with adaptive clock frequency are proposed, which result in a ratiometric digital output. To address the mismatch issue, two architectures, one with periodic swapping of the VFCs’ inputs and outputs, and the other with the use of a single analog-to-digital converter (ADC) as an analog front end, are developed. The concepts were demonstrated with implementations on a Zynq board (ZYBO). The results of the first architecture showed that for a 25% gain mismatch between the VFCs, the output gain error was reduced from around 7.4% to 0.79% and the offset error was reduced from around 11.8% to 0.01%. Additionally, for the second architecture, a maximum of 0.11% gain error and 0.1% offset error were recorded for an emulated ±25% supply drift.

A software-defined radio (SDR) for ultrawideband (UWB) communication systems places several stringent requirements on the analog-to-digital converter (ADC). One alternative to using a single ADC is to sample the received signal with an array of lower speed ADCs that were driven by interleaved sampling clocks; however, mismatches among the ADCs will result in signal distortion. This paper makes three important contributions to overcoming this problem: 1) analytical quantification of the impact of ADC gain, offset, and timing mismatches on the performance of a time-interleaved sampling ADC array for UWB signals; 2) demonstration of the efficacy of using a pilot-based matched-filter architecture to mitigate the impact of timing mismatches in the presence of multipath; and 3) implementation of an 8-ADC time-interleaved UWB SDR testbed that operates at an effective sampling frequency of 6.4 GHz. In addition, our findings allow for the design specification of the number of pilots required to obtain a desired system performance. The simulation and measured performance results from this paper demonstrate that ADC mismatches can be controlled to within plusmn10%, yielding acceptable levels of distortion and bit-error-rate (BER) performance on the UWB SDR testbed. Both analytical and simulation results also demonstrate the efficacy of a pilot-based matched filter in mitigating the impact of timing mismatch errors, even in the presence of multipath.

Synthetic instruments apply the flexibility and computational capabilities of a digital signal-processing platform to synthesize a wide variety of synthetic instruments. The emphasis presented in traditional descriptions of a synthetic instrument is the architecture and the capabilities of the digital signal processing (DSP) platform and the user interfaces to the same. In this paper we highlight and discuss considerations of the signal conditioning and signal collection tasks. The focal point of the signal collection process is the analog-to-digital converter (ADC), the element that defines the precision and the bandwidth of the sampled data representation of the signal processed by the DSP platform. Analog signal conditioning prior to the ADC performs the task of limiting the input signal bandwidth and possible translation of the spectral band center. Digital signal conditioning following the ADC continues to perform the same tasks by further limiting the bandwidth of the digitized input signal as well as performing spectral translation with appropriate sample rate changes. In addition, the post conversion process can correct gain, phase, and time delay imbalances between input signal paths as well as gain and phase distortion encountered in the analog signal path. We identify and address performance constraints of existing ADCs and present a number of signal processing-based options to enhance and extend the operating regimes of the analog signal conditioning and the ADC conversion process.

In this paper, anti-synchronization problem of two identical chaotic neural networks with time-varying delays is proposed. By using time-delay feedback control technique, mean value theorem and the Leibniz-Newton formula, and by constructing appropriately Lyapunov-Krasovskii functional, sufficient condition is proposed to guarantee the asymptotically anti-synchronization of two identical chaotic neural networks. This condition, which is expressed in terms of linear matrix inequality, rely on the connection matrix in the drive and response networks as well as the suitable designed feedback gains in the response network. Finally, the anti-synchronization of two chaotic cellular neural network and Hopfield neural network with time-varying delays are considered to illustrate the effectiveness of the proposed control scheme, in which, when compared with the nonlinear feedback control method, the proposed method shows superior performance. Key words: Lyapunov-Krasovskii functional, chaotic neural networks, anti-synchronization, time-varying delay, linear matrix inequality.