Performance Limits of Generalized Sampling Based 2-Channel Analog-to-Digital Converter

Abstract— A 2.5 V feed-forward second-order delta-sigma modulator for audio application is presented. A 9-level quantizer with a tree-structured dynamic element matching (DEM) was employed to improve the linearity by shaping the distortion resulted from the capacitor mismatch of the feedback digital-to-analog converter (DAC). A chopper stabilization technique (CHS) is used to reduce the flicker noise in the first integrator. The prototype delta-sigma analog-to-digital converter (ADC) implemented in a 65 nm 1P8M CMOS process occupies 0.747 mm 2 and achieves 109.1 dB dynamic range (DR), 85.4 dB signal-to-noise ratio (SNR) in a 24 kHz audio signal bandwidth, while consuming 14.75 mW from a 2.5 V supply. Index Terms —Delta-sigma modulator, feed-forward, dynamic element matching, chopper stabilization I. I NTRODUCTION Recent advances of CMOS technology have enabled the high quality signal processing in the multi-media and communication systems and have resulted in a great demand for the high resolution analog-to-digital converters (ADCs). Among various ADC architectures, the delta-sigma ADC offers high dynamic range by using oversampling and noise shaping properties. Moreover, as it requires only simple and relatively high-tolerance analog components with fast and complex digital signal processing to achieve high resolution, it is very well-suited for the digital CMOS process. The theoretical signal-to-quantization noise ratio (SQNR) of the delta-sigma ADC is given by Eq. (1)

High power consumption and hardware cost are the two challenges for practical massive MIMO systems. One promising solution is to employ low resolution analog to digital converter (ADC). In this paper, massive MIMO relaying systems are investigated with double resolution ADCs at base station receiver, where some antennas are connected to low resolution ADCs, while the rest of the antennas are connected to high resolution ADCs. Closed form expression for uplink spectral efficiency (SE) is derived using the maximum ratio combining receiver assuming perfect channel state information. Some asymptotic analysis is discussed to explore the effects of system parameters on SE such as; the number of receive antennas, ADC quantization bits, user transmit power and the rate of high precision ADC in double resolution ADC structure. Moreover, energy efficiency with some system parameters is studied. It is shown that the performance wastage owing to low precision ADCs can be recompensed by growing the number of receive antennas $$ \varvec{N} $$, following a logarithmic scaling law instead of increasing the transmit power at both of source and relay. The double resolution ADCs can achieve a better tradeoff between power consumption and SE when using 4 quantization bits. By using only around 30 antennas, the double resolution ADCs achieves its optimal energy efficiency for selecting system parameters.

A software-defined radio (SDR) for ultrawideband (UWB) communication systems places several stringent requirements on the analog-to-digital converter (ADC). One alternative to using a single ADC is to sample the received signal with an array of lower speed ADCs that were driven by interleaved sampling clocks; however, mismatches among the ADCs will result in signal distortion. This paper makes three important contributions to overcoming this problem: 1) analytical quantification of the impact of ADC gain, offset, and timing mismatches on the performance of a time-interleaved sampling ADC array for UWB signals; 2) demonstration of the efficacy of using a pilot-based matched-filter architecture to mitigate the impact of timing mismatches in the presence of multipath; and 3) implementation of an 8-ADC time-interleaved UWB SDR testbed that operates at an effective sampling frequency of 6.4 GHz. In addition, our findings allow for the design specification of the number of pilots required to obtain a desired system performance. The simulation and measured performance results from this paper demonstrate that ADC mismatches can be controlled to within plusmn10%, yielding acceptable levels of distortion and bit-error-rate (BER) performance on the UWB SDR testbed. Both analytical and simulation results also demonstrate the efficacy of a pilot-based matched filter in mitigating the impact of timing mismatch errors, even in the presence of multipath.

We have designed single-bit comparators and multi-bit flash analog-to-digital converters (ADCs) using three flavors of periodic comparators; one flavor uses a differential “quasi-one-junction” SQUID (DQOS) comparator, the second use a differential SQUID wheel comparator (DSW) and the third uses a symmetric differential SQUID wheel comparator (SDSW) with time-interleaved clocks. We have also developed a new performance analysis scheme that enables full reconstruction of input signal using a single-bit comparator. The signal is reconstructed based on multiple beat frequency measurements that track the position of the comparator thresholds in response to a dc offset to the input signal. In addition, to eliminate the frequency dependent distortions resulting from impedance mismatches over wide bandwidths, the signal and clock distribution network have been optimized using EM simulations. For distributing the clock signal to the multi-bit comparators, a 50 Ω coplanar transmission line has been designed. Test results for a 1-bit DSW comparator demonstrates a performance of 4.5 bits of resolution in Gray code for a beat frequency test using a 20 GHz input signal and 5.3 bits for 10 GHz input. 4 and 8-bit versions of the flash ADC with a DQOS comparator and a 3-bit time-interleaved ADC using the SDSW comparator have also been designed. The DQOS ADC has been tested up to 25 GHz input signal frequency with performance of 4.3 bits of resolution in Gray code for 19.7 GHz input signal. The time-interleaved ADC performance is 4.3 bits for a 15 GHz beat frequency test with an effective sampling rate of 30 GHz.

This paper presents a background timing skew calibration technique for time-interleaved analog-to-digital converters(ADCs). The timing skew between two adjacent sub- ADCs is detected in the digital domain through slope-based and statistics-based technique. Based on the detection error, the digitally controlled delay line(DCDL) is driven to minimum the timing skew. Using the proposed calibration algorithm in a 14- bit 500MS/s TI ADC model, the MATLAB simulation result shows a convergence time of 346ms under Nyquist frequency input with 1% oTs initial timing mismatch, and the proposed method can effectively reduce hardware consumption in circuit implementation.

Analog signals are converted into digital signals for digital signal processing. Analog-to-Digital Converter (ADC) is used for the conversion process. When required, Digital-to-Analog Converter (DAC) is used for reconverting the processed digital signals into analog signals. Sample-Hold amplifier, Anti-aliasing filter, Reconstruction filter and Operational amplifier (Op-amp) are the analog components that are generally used in signal conversion circuits. The operation of the analog components is presented. Four ADC architectures, namely, Flash ADC, Dual slope ADC, Successive approximation ADC and Sigma-Delta ADC, are explained. Two DAC architectures, namely, Binary-weighted input DAC and R-2R Ladder DAC, are explained.

본 연구에서 매우 정밀한 샘플링을 필요로 하는 고해상도 비디오 응용면을 위하여 병렬 파이프라인 아날로그 디지털 변환기(ADC)를 설계하였다. 본 ADC의 구조는 4 채널의 10-비트 파이프라인 ADC를 병력 time-interleave로 구성한 구조로서 이 구조에서 채널 당 샘플링 속도의 4배인 200MS/s의 샘플링 속도를 얻을 수 있었다. 변환기에서 핵심이 되는 구성요소는 Sample and Hold 증폭기(SHA), 비교기와 연산증폭기이며 먼저 SHA를 전단에 설치하여 시스템 타이밍 요구를 완화시키고 고속변환과 고속 입력신호의 처리론 가능하게 하였다. ADC 내부 단들의 1-비트 DAC, 비교기 및 2-이득 증폭기는 한 개의 switched 캐패시터 회로로 통합하여 고속동작은 물론 저 전력소비가 가능한 특성을 갖도록 하였다. 본 연구의 연산증폭기는 2단 차동구조에 부저항소자를 사용하여 높은 DC 이득을 갖도록 보강하였다. 본 설계에서 각 단에 D-플립플롭(D-FF)을 사용한 지연회로를 구성하여 변환시 각 비트신호를 정렬시켜 타이밍 오차를 최소화하였다. 된 변환기는 3.3V 공급전압에서 280㎽의 전력소비를 갖고 DNL과 INL은 각각 +0.7/-0.6LSB, +0.9/-0.3LSB이다. This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.

In this paper, we derive the achievable rate of single-carrier frequency domain equalizer (SC-FDE) and orthogonal frequency division multiplexing (OFDM) systems, constrained on low resolution analog to digital converters (ADCs). We assume that there is a full knowledge of channels at both transmitter and receiver sides. We model low resolution ADCs with an additive uniform quantization noise. We consider an ultra-wide band millimeter wave (mm-Wave) system with a frequency selective channel. The channel is based on practical results at mm-Wave frequencies. Our numerical results show that SC-FDE systems with minimum mean square error (MMSE) equalizers outperform OFDM and SC-FDE systems with zero forcing (ZF) equalizers at high signal to noise ratio (SNR) regimes. Moreover, benefits of increasing the ADCs resolution are not significant due to exponentially increment in the power consumption of ADCs.

Sample-time error among the channels of a time-interleaved analog-to-digital converter (ADC) is the main reason for significant degradation of the effective resolution of the high-speed time-interleaved ADC. A calibration technique for sample-time mismatches has been proposed and implemented at a low level of complexity. The calibration method uses random data and is especially suitable for ADCs used in digital data communication systems. An 800-MS/s four-channel, time-interleaved ADC system has been implemented to evaluate the performance of the technique. The experimental results show that the spurious-free dynamic range of the ADC system is improved to 58.1 dB at 350 MHz. The ADC system achieves a signal-to-noise and distortion ratio of 59.6 dB at 5 MHz and 50.1 dB at 350 MHz after calibration.

High-speed track-and-hold amplifier (THA) circuits are critical for high-speed, high-resolution data converters, particularly in emerging 100Gb/s optical communication systems. High-speed CMOS analog-to-digital converters (ADCs) have been demonstrated to 56GS/s, but the linearity tends to rapidly degrade at high frequency. The use of a high-speed THA can broaden the frequency response, improve the distortion performance, and mitigate some of the timing requirements for high-speed time-interleaved ADCs. Recent THA work has leveraged high-fmax Indium Phosphide (InP) HBTs to implement 50GS/s track-and-hold amplifiers. Nonetheless, a two-chip solution consisting of an InP THA and time-interleaved CMOS ADCs is extremely difficult to package while retaining high-speed performance.

A low power 10-bit 250-k sample per second (KSPS) cyclic analog to digital converter (ADC) is presented. The ADC's offset errors are successfully cancelled out through the proper choice of a capacitor switching sequence. The improved redundant signed digit algorithm used in the ADC can tolerate high levels of the comparator's offset errors and switched capacitor mismatch errors. With this structure, it has the advantages of simple circuit configuration, small chip area and low power dissipation. The cyclic ADC manufactured with the Chartered 0.35 μm 2P4M process shows a 58.5 dB signal to noise and distortion ratio and a 9.4 bit effective number of bits at a 250 KSPS sample rate. It dissipates 0.72 mW with a 3.3 V power supply and occupies dimensions of 0.42 × 0.68 mm2.

Modern wireless communication standards that support high rates of voice and video streaming need high-speed Analog-to-Digital Converters (ADCs) with wide Spurious-Free Dynamic Range (SFDR). Conventional time-interleaved ADCs suffer from spurious components that seriously affect the SFDR. In this paper, we present the mathematical background describing the effect of randomizing the samples among the interleaved ADCs and we propose a digitally oriented method based on this analysis to randomize the mismatches among the ADC channels. Analyses and simulations show the effectiveness of the proposed approach in multi-channel ADCs with arbitrary bit resolution, channel's number and sampling rate. For a 10-bit 500 MS/s ADC, the SFDR achieved using the proposed randomizing method can be as wide as 75 dB, which is an enhancement of more than 26 dB comparing to the conventional time interleaved ADC.

In this paper, an approach to estimate signal to noise ratio (SNR) and effective number of bits (ENOB) in nonideal multi-bit stages of pipelined analog to digital converters (ADCs) is presented. The most significant error sources in multistage ADCs are the capacitor mismatch and the finite and imprecise gain of amplifier. Output voltage of each stage in pipelined ADC is modeled by an ideal and a nonideal output, where nonideal output is the error due to circuit imperfections in each stage. Using an appropriate model, the SNR and ENOB due to circuit nonidealities and in terms of standard deviation of random errors are calculated. Simulation results show the accuracy of the analytical proposed approach in estimation of SNR and ENOB in multi-bit per stage pipelined converters.

To build a 16-bit audio delta-sigma (Δ-Σ) digital-to-analog converter (DAC), a low noise reconstruction filter has been presented in this paper. By using the direct charge transfer (DCT) technique, the low noise and small area is implemented. In addition, a fully differential operational amplifier (op-amp) with proposed switch capacitor (SC) common mode feed back (CMFB) circuit is employed for low-noise design in this system. The proposed reconstruction filter is designed in TSMC 0.35μm CMOS process. And a peak signal-to-noise density ratio (SNDR) of 95.3 dB and a dynamic range (DR) of 97.2 dB for a 5k Hz input signal is achieved at a 1.8V supply voltage.

The analog-to-digital converter (ADC) represents a fundamental bottleneck in power- and cost-efficient realizations of “mostly digital” communication transceivers at multi-Gigabit speeds. Time-interleaved (TI) ADCs, with slower, power-efficient “sub-ADCs” employed in parallel to obtain a high-rate ADC, represent a potential solution to this bottleneck. The performance floor caused by mismatch in TI-ADCs can be eliminated by estimating and correcting for the mismatch. For TI-ADCs employed in communication receivers, prior work has shown that mismatch and channel parameters can be estimated jointly by using the training available in communication systems. In this paper, we propose simplified algorithms for this purpose, and examine how well they scale as the number of sub-ADCs gets large. We conclude that rapid convergence can be attained if the training sequence scales with the number of sub-ADCs, and that the convergence rate can be significantly enhanced by a suitable choice of periodic training sequence.