A basic mathematical formalism for representation and analysis of RF/microwave EDA and design flows

Physical analog IC design has not been automated to the same degree as digital IC design. This shortfall is primarily rooted in the analog IC design problem itself, which is considerably more complex even for small problem sizes. Significant progress has been made in analog automation in several R&D target areas in recent years. Constraint engineering and generator-based module approaches are among the innovations that have emerged. Our paper will first present a brief review of the state of the art of analog layout automation. We will then introduce active and open research areas and present two visions -- a "continuous layout design flow" and a "bottom-up meets top-down design flow" -- which could significantly push analog design automation towards its goal of analog synthesis.

Placement is an important step in modern very-large-scale integrated (VLSI) designs. Detailed placement is a placement refining procedure intensively called throughout the design flow, thus its efficiency has a vital impact on design closure. However, since most detailed placement techniques are inherently greedy and sequential, they are generally difficult to parallelize. In this article, we present a concurrent detailed placement framework, ABCDPlace, exploiting multithreading and graphic processing unit (GPU) acceleration. We propose batch-based concurrent algorithms for widely adopted sequential detailed placement techniques, such as independent set matching, global swap, and local reordering. The experimental results demonstrate that ABCDPlace can achieve $2\times $ – $5\times $ faster runtime than sequential implementations with multithreaded CPU and over $10\times $ with GPU on ISPD 2005 contest benchmarks without quality degradation. On larger industrial benchmarks, we show more than $16\times $ speedup with GPU over the state-of-the-art sequential detailed placer. ABCDPlace finishes the detailed placement of a 10-million-cell industrial design in 1 min.

In this paper we propose a distributed system LSI design environment where both LSI designers and CAD tool developers/ engineering can collaboratively work for higher performance designs. What we propose is a framework where not only design issues but also CAD tool related problems can be simultaneously taken care of by both designers and CAD engineers. Traditional design tools and flows are assuming to use CAD tools which have been fully developed and cannot be modified or enhanced when designing LSI chips. In order to use the most advanced LSI technology, however, it is essential to use the most advanced CAD tools which may not be fully debugged and tuned yet. This means that CAD tools must be enhanced when designing a new advanced LSI chip. Also we briefly discuss about implementation issues of the proposal on top of Croquet type distributed environments by showing a debugging process of hardware logic designs. We define consistency conditions on the use of CAD tools for the target LSI design flows including interface issues among various CAD tools used in the design flow and analyze them with a method similar to model checking type approaches used in formal analysis. We define virtual shared screens for both LSI designers and CAD developers/engineers collaboration and monitors activities on them, which will be the base of our model checking type analysis. We examine various issues including interface checking among CAD tools, interface checking among design blocks, and tool performance enhancement/ design modifications.

In Chap. 2 we covered technologies and in Chap. 3 we saw how these technologies interface with physical design. Here in Chap. 4 we now provide an end-to-end overview of the physical design process, namely how to physically construct the layout of an electronic circuit. In this chapter we present the fundamental knowledge an engineer must possess to carry out this task. In Chap. 5 we then discuss each of the specific physical design steps in further detail. We begin the chapter by introducing the design flow (Sect. 4.1), design models (Sect. 4.2) and design styles (Sect. 4.3). Next, we investigate various design tasks and related tools (Sect. 4.4), before discussing optimization goals and design constraints (Sect. 4.5). Up to this point our treatise has focused mainly on the digital design flow. In Sect. 4.6 we introduce the characteristics of, and differences between, analog, digital, and mixed-signal design flows. Looking toward the future, we conclude the chapter by presenting two different yet complementary visions for analog-design automation to overcome the analog-digital design gap (Sect. 4.7).

The previous chapters described the basic principles for the application channel coding. Before proceeding to advanced channel coding techniques and its possible hardware realization we will introduce in this chapter the basic steps for a hardware design. An entire receiver is large system and comprises many different functionalities. Combining all of them on a single die yields a so called System-on-a-Chip (SoC). The SoC design requires the knowledge from system specification down to hardware partitioning and refinement. However, every SoC is partitioned in smaller functional blocks which can then be developed individually on component level. This is especially true for the channel decoder which is just one single component in a larger system. The same hold for e.g. demodulator, source encoder or decoder and so on. The advantage of designing components individually is that typically the functionality is restricted and can be well described. In this chapter we first revise (Sect. 4.1) the design flow for a single component and show the different design constraints which are posed either by the communications domain or the hardware domain. Note, that the design flow shown here is no general hardware design flow. It is restricted to communications specific constraints with respect to the introduced base band processing components. Memories are an extremely important part for the entire SoC and for each individual component as well.

Multi-agent organizational modeling frameworks can be considered as an efficient solution regarding the distributed applications’ problems such as task bundle mechanisms, supply chain management, as well as air traffic control. The main objective of this paper is to provide a solution based on a solid mathematical theory for the modeling, the analysis and the verification of artificial organizations properties, and particularly those of Multi-Agent Systems (MASs). Category theory is a mathematical formalism used to categorically study the logics of organizations in different societies. Therefore, it can be projected on artificial organizations in a categorical way. Our work is revolved around the idea of modeling Multi-Agents organization using category theory. In other words, it consists on the transformation of Agent-Group-Role (AGR) organizational model in a categorical way in order to obtain a formal semantics model describing the MAS organization. This formal model allows the analysis, the verification and also the validation of the main concepts of an organization at a high level of abstraction

Mixed-signal design becomes more and more popular nowadays, designers are required to quickly integrate IPs and run through the design flow to tape out in short time, so a fast and accurate design flow will be critical to ensure the success of the project. In this paper, a UVM-based methodology for mixed-signal sub-system verification of wireless power receiver family MCU is introduced. As standard digital functional verification method, UVM co-works with analog design which greatly improves the verification efficiency and quality. The model-based verification approach also helps build a scalable and re-usable framework, in which coverage driven verification (CDV) is achieved with automatic stimulus generation, analog assertions are also used to monitor and verify mixed-signal system behavior automatically.

Electronic teaching is a task that intents to also prepare the student to understand and design analog and digital circuits. However the design flow in those two arenas are quite opposite as result of very different development state and also are the design methodologies, being challenging for both teachers and students. In fact, the electronic design in the digital field is centered in the use of components based in two kind of circuits (microprocessor and FPGA) using a relatively high level programing/configuring languages. In an opposite way, the analog design is traditionally founded in the use of elementary components (e.g. resistors and capacitors) associated with macroblocks (e.g. operational amplifiers) in order to built-up the wanted mission circuit. However they have just a few analog programmable components, as the PSoC that is analogically configurable in a similar manner that the one already used in the digital domain. The use of this kind of components, however, is not straightforward being necessary to get some concepts traditionally not taught in the analog electronic classes. The training using PSoC are then indispensable to verify if the programed analog circuit corresponds to the intended one. The current work present an innovative remote lab to support teaching of the PSoC.

Recent developments in wide bandgap analog and mixed-signal IC design will be described including example circuits such as amplifiers, data converters, controllers, and protection circuits and their integration into power electronic platforms. The paper overviews the design flow for both IC design and heterogeneous integrated power electronics. A synthesis tool under development for heterogeneous power circuit layout will be briefly described as a capstone to the application space descriptions. Advances in semiconductor device modeling of low-voltage SiC MOSFETs will be described as well.

An application-specific instruction-set processor (ASIP) is a technique that exploits special characteristics of application(s) to meet the desired performance, cost and power requirements. The generation and selection of Application-Specific Instructions (ASIs) dramatically affect the quality of an ASIP with design constraints such as number of register file I/Os and hardware cost. In this paper, a design flow is developed to automatically combine the disjoint operations as an ASI to enrich the selection varieties. The operation cover-ratio and the ASI latency model are used to select profitable ASIs so that the performance can be improved. The experimental results show the maximal 1.64x speed up can be obtained under hardware cost less than 8000 LEs in Altera FPGA.

Summary form only given, as follows. The tutorial presents an introduction into "DfY/DfM - Design for Yield and Manufacturability" covering basics of analogue circuit simulation, statistical analysis and design centering from both methodology/implementation as well as from the industrial application side. The tutorial presents the following six topics: introduction into DfY/DfM, basics of analogue circuit simulation, methodology for statistical circuit analysis and yield optimisation, software solutions and design flow integration, design flow specific industrial applications and use cases closing with an outlook on actual and future challenges in the DfY/DfM area regarding a global design environment. Intended audience: analogue- and mixed-signal circuit designers, CAD- and design-support engineers (library management, technology migration and design reuse, process characterisation)

In physical modeling of phonation, the pressure drop along the glottal constriction is classically assessed with the glottal geometry and the subglottal pressure as known input parameters. Application of physical modeling to study phonation abnormalities and pathologies requires input parameters related to in vivo measurable quantities commonly corresponding to the physical model output parameters. Therefore, the current research presents the inversion of some popular simplified flow models in order to estimate the subglottal pressure, the glottal constriction area, or the separation coefficient inherent to the simplified flow modeling for steady and unsteady flow conditions. The inverse models are firstly validated against direct simulations and secondly against in vitro measurements performed for different configurations of rigid vocal fold replicas mounted in a suitable experimental setup. The influence of the pressure corrections related to viscosity and flow unsteadiness on the flow modeling is quantified. The inversion of one-dimensional glottal flow models including the major viscous effects can predict the main flow quantities with respect to the in vitro measurements. However, the inverse model accuracy is strongly dependent on the pertinence of the direct flow modeling. The choice of the separation coefficient is preponderant to obtain pressure predictions relevant to the experimental data.

The mature electronic design automation (EDA) tools and well-defined abstraction-levels for digital circuits have almost automated the digital design process. However, analog circuit design and optimization is still not automated. Custom design of analog circuits and slow analog in SPICE has always needed maximum efforts, skills, design cycle time. This paper presents a novel design flow for constrained optimization of nano-CMOS analog circuits. The proposed analog design flow combines polynomial-regression based models and genetic algorithm for fast optimization. For evaluating the effectiveness of the proposed design flow, power minimization in a 50nm CMOS based current-starved voltage-controlled oscillator (VCO) is carried out, while treating oscillation frequency as a performance constraint. Accurate polynomial-regression based models are developed for power and frequency of the VCO. The goodness-of-fit of the models is evaluated using SSE, RMSE and R <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Using these models, we form a constrained optimization problem which is solved using genetic algorithm. The flow achieved 21.67% power savings, with a constraint of frequency ≥ 100 MHz. To the best of the authors' knowledge, this is the first study which approaches a VCO design problem as a mathematical constrained optimization involving the usage of regression based modeling and genetic algorithm.

Coupling Of Synthesis And Layout: Challenges And Solutions

considered which are expressed using equations, inequalities, and intervals and also mixed combinations of these. Up to now no analogue design tool makes use of interval arithmetic in which different kind of constraints can be handled easily. This introduces a lot of exception handling and often causes unnecessary reduction of solution space already in the beginning of synthesis without a chance of finding a solution at lower levels. Further problems are presented by dependencies between connected cells, macros and primitives. A progress in analogue design automation has occured with appearence of the synthesis tool ARIADNE [6]. It uses a more global approach to analogue circuit synthesis. In ARIADNE a clear separation between design knowledge and general design procedures has been made. Critical point in this concept is, however, the high computation effort for handling the design constraints. This paper presents a new strategy for synthesis of analogue circuits in expert systems with an expert oriented approach to solving analogue design problems. Analogue circuits are hierarchically synthesised in a topdown manner while focusing on the main features of cells and subcells. This reduces drastically problems known in existing concepts, which involve implementation, expansion, and maintenance of expert knowledge, transparency of decisions, and application dependency.