A BiCMOS 50 MHz cache controller for a superscalar microprocessor

Design methodologies for Hitachi's RISC microprocessors and microcontrollers are discussed. One of the processors is a high-end PA-RISCTM. The others, the PA/50 and the SH series microcontroller, are low power and low cost processors. Low cost processors require small chip sizeand short design time. To shorten the architecture level design time, we have developed a RT-level behavior simulation tool based on C language. And to reduce the total design time, we use a gate-level synthesis program from the behavior model description. This approach resulted in the low power 42 MIPS/W PA-RISCTM processor (the PA/50, which run at a 33 MHz clock rate) being completed within 15months. Another approach to minimizing chip size while maintaining high performance is to reduce the design turnaround time by using microcode instead of direct wired logic design. We wrote 480-word microcodes equivalent to a 5.8K transistor logic. After assigning the control stages for the microcode fields, we used an in-house logic synthesis and optimized for performance and chip size. The CPU core of the SH series microcontroller occupies only 8 mm2 including CPU core and multiplier circuit. The processor reaches 16 MIPS at 20 MHz. It took 17 man-months to realize a minimum 8 mm2 chip. The total control logic consists of 27 thousand transistors.

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Multithreading and multicore processing are powerful ways to take advantage of parallelism in applications in order to boost a system's performance. However, exploring sufficient parallelism and achieving data locality with low communication overhead are still important research issues in embedded multithreading/multicore design. This paper introduces the design of a fast data switching mechanism between multilevel storage structures in a new multicore architecture. This paper makes several contributions to the development of contemporary sophisticated multimedia applications with advanced standards such as H.264. The first contribution, <emphasis emphasistype="italic">collaborative-multithreading</emphasis>, tightly unifies reduced instruction set computer and collaborative multithreading digital signal processing (DSP) in order to exploit high parallelism to provide sufficient computing power to applications. Each collaborative thread of our DSP is constructed by a heterogeneous-simultaneously multithreading single instruction, multiple data structure, and four media processing cores, which is connected by a fast switch for providing a fast data exchange mechanism among correlative streams on a thread-level basis. Our second contribution is <emphasis emphasistype="italic">one-stop streaming processing</emphasis>, which aims to keep data in the system for as long as possible until it is no longer needed, thus making data more efficient to access. Our third contribution is a <emphasis emphasistype="italic">chunk threading programming model</emphasis>, including a thread management library and threading communication directives for reducing data communication and synchronization overhead. By a combination of coarse-grained and fine-grained threading, programmers can choose various threading levels based on the amount of data exchange in a program. With our proposed techniques and an appropriate programming model, we can reduce processing time by 54.9% in H.264 video encoding (common intermediate format video at 16.574 f/s) with the 1-virtual independent and streaming processing by open collaborative multithreading configuration, compared to the Texas Instruments C62 core that owns 8 function units. We realize our design as a prototype by chip implementation, and fabricate it as a chip based on the Taiwan Semiconductor Manufacturing Company Ltd. 0.13 <formula formulatype="inline"><tex Notation="TeX">$\mu {\rm m}$</tex></formula> process. The die size of the processor core is 16.12 <formula formulatype="inline"><tex Notation="TeX">${\rm mm}^{2}$</tex></formula>, including 414 k logic transistors and 34.4 kB of on-chip static random access memory. The processor runs at 180 MH0z/1.2-V and consumes 245 mW by postsimulation results. </para>

In this paper a multiprocessor system with a two-level cache hierarchy is modeled and extensions of two write invalidate snoopy protocols are implemented in the L2 cache controller for coherence maintenance. The paper focuses on the use of different techniques for reducing miss penalty and a comparative performance study is done for each possibility. To solve efficiently a miss read, the early restart technique is implemented in the second level of cache hierarchy and the critical word first technique is used in the first level cache controller. To obtain better performance in the case of a write miss the write allocate technique is implemented at the L2 cache controller. Two models, with different L1 cache controllers are considered in our study, one of them using the non-write allocate technique and the other using the write allocate. We show that the write allocate and non-write allocate techniques are independent over the processors number. The major conclusion of this work is that the non-write allocate technique is not only less complex for implementation but also better in performance if the L1 write miss rate represents a high percentage of L1 miss rate.

This superscalar microprocessor is the first implementation of a 32-bit RISC architecture specification incorporating a single-instruction, multiple-data vector processing engine. Two instructions per cycle plus a branch can be dispatched to two of seven execution units in this microarchitecture designed for high execution performance, high memory bandwidth, and low power for desktop, embedded, and multiprocessing systems. The processor features an enhanced memory subsystem, 128-bit internal data buses for improved bandwidth, and 32-KB eight-way instruction/data caches. The integrated L2 tag and cache controller with a dedicated L2 bus interface supports L2 cache sizes of 512 KB, 1 MB, or 2 MB with two-way set associativity. At 450 MHz, and with a 2-MB L2 cache, this processor is estimated to have a floating-point and integer performance metric of 20 while dissipating only 7 W at 1.8 V. The 10.5 million transistor, 83-mm/sup 2/ die is fabricated in a 1.8-V, 0.20-/spl mu/m CMOS process with six layers of copper interconnect.

The performance of a system, especially multiprocessor system, heavily depends upon the efficiency of its bus architecture. In System-on-a-Chip (SoC), the bus architecture can be devised with advantages such as shorter propagation delay (resulting in a faster bus clock), larger bus width, and multiple buses. This paper presents five different SoC bus architectures for a multiprocessor system: Global Bus I Architecture (GBIA), Global Bus II Architecture (GBIIA), Bi-FIFO Bus Architecture (BFBA), Crossbar Switch Bus Architecture (CSBA), and CoreConnect Bus architecture (CCBA). The performance of these architectures is evaluated using applications from wireless communications-an Orthogonal Frequency Division Multiplexing (OFDM) transmitter-and from video processing-an MPEG2 decoder. To increase performance, these bus architectures employ a pipelined scheme, resulting in improved throughput. While all five bus architectures perform well, we find that BFBA and CSBA perform the best for the OFDM transmitter and the MPEG2 decoder, respectively.

This paper presents a real-time and cost effective method for sensing moving objects on the freeway. Based on the proposed method, we can evaluate the traffic rate of vehicles, the speed of moving objects and distinguish the kind of vehicle using their length. It is different from the conventional vehicle detection systems that need expensive hardware architecture, such as the multiprocessor system and VME bus, to implement the complicated algorithm. We develop an efficient and simple algorithm that has been successfully installed in a general industrial IBM-compatible PC. The two trigger lines policy is proposed to reduce the computation time of this system. Because there is an error signal due to the difference between the moving objects and that of the background on the trigger line, we construct a formal grammar to describe these pulse-like error signals based on the compiler's technique in the software engineering. Therefore, the system states can be easily derived by the semantic routines. To overcome the brightness of day/night-switching and the cover of cloudy shadow, etc., we use a novel adaptive neural network to train the grey level of the background, and then the system parameters can be adapted quickly. The analyzer is called VSS (Vehicle Supervising System), and has been developed and tested on the freeway between Taipei and Lin-Ko City in Taiwan. >

Signal integrity and associated optimization techniques in power delivery network for multi-core processors, whether powered by a single converter or several power converters, are discussed. The high integration of the multi-core processors on a single die makes chipset's sensitivity to crosstalk noise more likely. Several power converters in a multi-core processor system could improve energy efficiency and dynamic performance among others. However, this paper focuses on how several power converters can be used to achieve over 60dB of crosstalk noise isolation. Crosstalk noise can be reduced by dedicating a power converter for each processor core (or more) and placing the power converters between the processors cores.

Parallelization of a Monte Carlo particle transport simulation code

Low-power content addressable memory (CAM) array for mobile devices

The trend in multicore processors indicates that all future processors will be multicore, and hence the future cloud systems are expected to have nodes and clusters based on multicore processors. On the application front, to utilize these multicore processors, most future applications are expected to be parallel programs. Gang scheduling is a popular strategy of scheduling parallel programs on multiprocessor systems. ‘Adaptive First-Come-First-Served’ and ‘Largest-Gang-First-Served’ are most popular gang scheduling algorithms, but they are susceptible to starvation and hence high variance in response time. To address starvation, process migration mechanisms have been proposed in the literature. Migrating a process to a new processor is generally expensive, and also it does not eliminate starvation. This paper presents a starvation free gang scheduling algorithm for multicore processors without using process migration. The algorithm is simple, fair, and efficient.

The number of chip pins is limited due to the cost and reliability issues of sophisticated packages, and it is predicted that the chip pin count will be overstretched to satisfy the requirements of both power delivery and memory access. The gap between the achievable pin count and the demand will increase as the technology scales, due to the increasing computation resources and supply current. Pin reduction techniques are thus required for continued computing performance growth. In this article, we propose a chip pin constraint alleviation strategy, through on/off-chip power delivery system co-design, to effectively reduce the demand for power pins. An analytical model of a power delivery system, consisting of on/off-chip regulators and a power delivery network, is proposed to evaluate the influence of regulator design and package conduction loss. By combining this model with a multi-core processor model of performance and memory bandwidth requirements, we characterize the entire multi-core processor system to investigate the relationship between the chip pin constraint and performance in multi-core processor scaling and the effectiveness of our strategy. Experiments show that with the conventional power delivery system design, the chip pin constraint severely limits the performance growth as the technology scales. Using the on/off-chip power delivery system co-design, our strategy achieves a significant pin count reduction, for example, 31.3% at the 8nm technology node, compared to the conventional design with the same chip performance, while, provided with the same chip pin count, it is able to improve, by 35.0%, the chip performance at 8nm compared to the conventional design. For real applications of different parallelism, our strategy outperforms its counterpart, with a 23.7% performance improvement on average at the 8nm technology node.

With the advent of multi-core processors, parallel execution of multiple tasks has become a common practice. Various scheduling algorithms have addressed this issue considering multiprocessor systems. Most of these algorithms target application level parallelism. Task level parallelism within an application can be exploited using shared memory architecture such as multi-core processor or in a distributed computing environment. In this paper, we propose a static scheduling algorithm that generates a schedule that can be optimized for one or all parameters including execution time, number of processors, and efficiency of processors. The input to this scheduler is a task dependency matrix is generated using dependency analysis technique. Efficiency of this scheduler is high because it uses multiple parameters such as task wait time, number of tasks whose dependency gets resolved by scheduling a task, and task execution time. The paper concludes with an example of applying this technique to a set of tasks.

This paper presents an efficient pipelined broadcasting algorithm with the inter-node transmission order change technique considering the communication status of processing nodes. The proposed method changes the transmission order for the broadcast operation based on the communication status of processing nodes. When a broadcast operation is received, a local bus checks the remaining pre-existing transmission data size of each processing node; it then transmits data according to the changed transmission order using the status information. Therefore, the synchronization time can be hidden for the remaining time, until the pre-existing data transmissions finish; as a result, the overall broadcast completion time is reduced. The simulation results indicated that the speed-up ratio of the proposed algorithm was up to 1.423, compared to that of the previous algorithm. To demonstrate physical implementation feasibility, the message passing engine (MPE) with the proposed broadcast algorithm was designed by using Verilog-HDL, which supports four processing nodes. The logic synthesis results with TSMC 0.18 μm process cell libraries show that the logic area of the proposed MPE is 2288.1 equivalent NAND gates, which is approximately 2.1% of the entire chip area. Therefore, performance improvement in multi-core processors is expected with a small hardware area overhead.

Different cores typically share the last-level cache in a multi-core processor. Threads running on different cores may interfere with each other. Therefore, the multi-core worst-case execution time (WCET) analyzer must be able to safely and accurately estimate the worst-case inter-thread cache interference. This is not supported by current WCET analysis techniques that manly focus on single thread analysis. This paper presents a novel approach to analyze the worst-case cache interference and bounding the WCET for threads running on multi-core processors with shared L2 instruction caches. We propose to use an interference matrix to model inter-thread interference, on which basis we can calculate the worst-case inter-thread cache interference. Our experiments indicate that the proposed approach can give a worst-case bound less than 1%, as in benchmark fib-call, and an average 16.4% overestimate for threads running on a dual-core processor with shared-L2 cache. Our approach dramatically improves the accuracy of WCET overestimatation by on average 20.0% compared to work.

Multicore systems oftentimes use multiple levels of cache to bridge the gap between processor and memory speed. This paper presents a new design of a dedicated pipeline cache memory for multicore processors called dual port content addressable memory (DPCAM). In addition, it proposes a new replacement algorithm based on hardware which is called a near-far access replacement algorithm (NFRA) to reduce the cost overhead of the cache controller and improve the cache access latency. The experimental results indicated that the latency for write and read operations are significantly less in comparison with a set-associative cache memory. Moreover, it was shown that a latency of a read operation is nearly constant regardless of the size of DPCAM. However, an estimation of the power dissipation showed that DPCAM consumes about 7% greater than a set-associative cache memory of the same size. These results encourage for embedding DPCAM within the multicore processors as a small shared cache memory.