A novel real-time analyzer for moving objects on freeway

A description is given of a BiCMOS 50-MHz, 2.2 M-transistor cache controller (CC) chip which supports up to 2 MB of direct-mapped secondary cache for a superscalar microprocessor chip (PU) and interfaces with two multiprocessor (MP) buses. One is the MBus, a circuit-switched MP system bus operating at TTL (transistor-transistor logic) levels. The other is the XBus, a local packet-switched bus operating at either TTL or Gunning-transceiver logic (GTL) levels. In XBus mode, the CC connects to MP buses through buswatcher chips, up to four of which can be connected to the CC to support 4 MP buses. With XBus interface, the CC can support customized MP buses. >

In some real practical and industrial applications, output signal sampling and input signal updating are performed with different rates because of technological constraints. Thus, a large number of existing systems are dual-rate or multi-rate. Identifying parameters of such systems is of great importance. In this paper, we identify parameters of a dual-rate observable canonical system. Since parameters and system states are not known simultaneously, Kalman filter and least squares error method are combined. Parameters are identified with least squares error method and states are estimated using Kalman filter. In this paper, two different algorithms are proposed. In the first algorithm, interpolation is employed to calculate output at instants which are not accessible. In the second algorithm, an auxiliary model is used to obtain output. Finally, in a simulation, parameters of a system are estimated using these algorithms and their results are compared.

Blood oxygen saturation is an important parameter of the respiratory system, and its monitoring is crucial during clinical ambulance operations, but the accuracy and integration of current oximeters need to be improved. In order to cope with the inevitable noise interference in the oximetry detection, the current oximetry monitors often use Kalman filtering FIR filtering, and other algorithms to optimize the detection signal. However, these filters have certain limitations in dealing with ambient light changes and different scenarios. For this reason, this paper proposes an adaptive filtering algorithm. In this algorithm, in a specific signal - processing situation, the noise signal is superimposed on the original signal after the unknown system undergoes a linear change, thus forming the desired signal. The noise signal enters the adaptive filter as an input, and the adaptive algorithm inside the filter makes the noise signal as close as possible to the state of the unknown system in the natural environment and generates an output signal. The noise in the desired signal is canceled out by the negative feedback mechanism and an error signal is obtained. The error signal is fed back to the adaptive filter, which updates its weights and then continues with the next filtering operation, and so on to achieve continuous optimization of the signal.

Fault-Tolerant Recursive Least-Squares Computations on a Mesh-Connected Parallel Processor

The drastically reduced costs and improved performance of fiber optic components in recent years offers an opportunity to economically incorporate high-bandwidth optical communication links within a large-scale multiprocessor system. In this paper, the design, implementation, and initial performance of a fiber optic bus for a tightly coupled multiprocessor system are discussed. This optical bus ulitizes a multiple fiber-multiple star configuration with data rates of up to 80 MHz. It transmits bus control line information by repetitively scanning the control lines and transmitting their states as a packet of bits. It is currently being used for a 30-processor system called the Heidelberg Polyp, which has a custom bus design. However, the design approach is a general one that could easily be adapted to other buses, especially asynchronous buses such as the VME bus.

Simultaneous Estimation of Innovation Variance and States in a Dynamic System

On-chip communication architecture plays an important role in determining the overall performance of the System-on-Chip (SoC) design. In the recourse sharing mechanism of SoC, the communication architecture should be flexible to offer high performance over a wide range of traffic. The paper describes and evaluates the use of fuzzy logic arbiters for shared-bus multiprocessor system. In such systems, arbiters are used to resolve conflicts between processor requests shared bus. Typically, these conflicts are resolved by using two-stage arbitration schemes that employ policies such as random choice, daisy chaining, round-robin, etc. A new way of implementing these arbiters is the use of fuzzy logic to resolve resource request conflicts based on the system state and performance variables. This paper proposed a new technique for implementation of fuzzy logic in the system arbiters and presents a simulation program. The inputs are fuzzified by using appropriate membership functions, and rules have been defined in such a way as to increase and distribute evenly the acceptance rate of each processor in the system

Consumer electronics today such as cell phones often have one or more low-power FPGAs to assist with energy-intensive operations in order to reduce overall energy consumption and increase battery life. However, current techniques for programming FPGAs require people to be specially trained to do so. Ideally, software engineers can more readily take advantage of the benefits FPGAs offer by being able to program them using their existing skills, a common one being object-oriented programming. However, traditional techniques for compiling object-oriented languages are at odds with todays FPGA tools, which support neither pointers nor complex data structures. Open until now is the problem of compiling an object-oriented language to an FPGA in a way that harnesses this potential for huge energy savings. In this paper, we present a new compilation technique that feeds into an existing FPGA tool chain and produces FPGAs with up to almost an order of magnitude in energy savings compared to a low-power microprocessor while still retaining comparable performance and area usage.

Task assignment in a multiprocessor system

Problem statement. Gas distribution systems of settlements are compound complexes, the main task of which is the reliable and safe supply of gas to consumers. Most of the existing gas distribution systerms of settlements have reached their maximum service life, therefore an important task is to modernize and reconstruct them using the latest technologies of the renovation of pipeline systems. In addition, the number of emergencies has recently increased due not only to the ageing of the system components but also to the destruction of gas pipelines as a result of russian aggression. To make informed and effective decisions on the restoration, reconstruction or modernization of gas supply systems, it is necessary to assess their actual technical condition, namely, their operability. The operability of an operating gas pipeline is determined on the basis of a database of its technical condition, namely: executive documentation, drawings and passports of gas pipelines, route schemes, defect lists, certificates of pipes and welded joints, capacity, etc. Moreover, gas supply systems are complex and dynamic, therefore a systematic approach is needed to determine operability as a state by which the ability to perform specified functions is assessed, according to the reliability theory. The purpose of the article − is to systematize the states of gas distribution networks according to their operability to determine the expediency and method of reconstruction (modernization) of the systems. Conclusion. The article proposes a systematization of the states of gas distribution systems according to their operability. The decision on the need and type of reconstruction (modernization) of gas distribution systems should be made depending on the state of the systems' operability. This will allow to minimize the cost of reconstruction and obtain optimal system parameters.

The performance of a system, especially multiprocessor system, heavily depends upon the efficiency of its bus architecture. In System-on-a-Chip (SoC), the bus architecture can be devised with advantages such as shorter propagation delay (resulting in a faster bus clock), larger bus width, and multiple buses. This paper presents five different SoC bus architectures for a multiprocessor system: Global Bus I Architecture (GBIA), Global Bus II Architecture (GBIIA), Bi-FIFO Bus Architecture (BFBA), Crossbar Switch Bus Architecture (CSBA), and CoreConnect Bus architecture (CCBA). The performance of these architectures is evaluated using applications from wireless communications-an Orthogonal Frequency Division Multiplexing (OFDM) transmitter-and from video processing-an MPEG2 decoder. To increase performance, these bus architectures employ a pipelined scheme, resulting in improved throughput. While all five bus architectures perform well, we find that BFBA and CSBA perform the best for the OFDM transmitter and the MPEG2 decoder, respectively.

Processor scheduling policies for multiprocessor systems can be broadly divided into space-sharing and time-sharing policies. Space-sharing policies divide the system processors into a number of partitions and each partition is exclusively allocated to a single job. In time-sharing policies, processors are temporally shared by jobs. Several space-sharing and time-sharing policies have been proposed for small-scale shared-memory systems and require a central run queue and/or central scheduler. The central queue scheduler poses serious scalability problems for large-scale multiprocessor systems. Furthermore, space-sharing and time-sharing policies have their advantages and disadvantages. In this paper, we propose a new multiprocessor scheduling policy that eliminates contention for the central queue/scheduler. Our hierarchical scheduling policy (HSP) is a self-scheduling policy and uses a hierarchical run queue organization to facilitate processor allocation to jobs. We show that the HSP policy is considerably better than purely space-sharing and purely time-sharing policies over a wide range of system and workload parameters of interest.

Pseudo-wavelets were proposed for system identification of linear systems to determine their natural frequencies and modal damping ratios. The approach provides excellent results for single-degree-of-freedom (SDOF) oscillators but significant errors might be observed for multiple-degree-of- freedom (MDOF) systems due to interference between different modes if the pseudo-wavelet transform (PWT) is directly applied. IN this paper a truncated pseudo-wavelet transform was employed to improve the accuracy for MDOF systems. A peak of the Fourier amplitude spectrum of the response was located and truncated in its neighborhood to isolate the peak. The frequency amplitude response function of a linear SDOF system was selected as the pseudo-wavelet. A truncated pseudo-wavelet transform was performed and its maximum value was located on a contour map of the PWT coefficients. The associated frequency and bandwidth of the MDOF system may be identified by the matching values of the scale and shift parameters. The methodology is illustrated for linear MDOF systems to identify their system parameters and good estimates were obtained. Noise effects were discussed. The approach can be applied for structural health monitoring. Change in system parameters using any two segments of response data may suggest occurrence of structural damages.

In this paper, a fine-grained scheduling approach to enhance lifetime reliability of multiprocessor systems is presented. Lifetime reliability is an important and emerging concern arising with advances in technology due to the increase in power density. As a result, temperature variation accelerates wear-out, leading to system failures. The antagonistic relation of lifetime reliability with other design parameters of multiprocessor systems, such as power consumption and temperature, makes its improvement more challenging. Lifetime reliability enhancement approaches are considered at different levels of abstractions and for various system components. Our proposed scheduling method extracts the precise low-level information of lifetime reliability from determined blocks of processing cores and utilizes them at system-level to study the system state criticality at a low-performance cost. Based on the online periodic monitoring, our proposed scheduling approach applies control actions to improve lifetime reliability of the system according to its effective parameters. To demonstrate the effectiveness of our proposed scheduling approach in improving lifetime reliability and compare it to the previous related research, several experiments are considered. To simulate the target multiprocessor system and the proposed approach, the Enhanced Super ESCalar (ESESC) simulator for computer architecture tool is utilized. The experimental results show that employing our proposed scheduling method improves lifetime reliability at about 54[Formula: see text]. Moreover, it causes 14% and 12% enhancement in temperature and power consumption. Furthermore, we perform a Monte Carlo-based simulation to validate the proposed scheduling approach and generalize it to other applications at very low-performance overhead. Experimental results show that Monte Carlo simulation extremely decreases the execution time rather than ESESC which makes utilizing our scheduling approach reasonable in large applications.

A pixellated germanium Compton camera is currently being developed for imaging 511 keV sources in nuclear medicine. It was built by ORTEC and consists of two planar Ge detectors (the scatter and the absorption detector) housed within the same cryostat. The scatter and absorption detectors have 152 and 25 4/spl times/4 mm/sup 2/ pixels respectively. The readout electronics was developed at Daresbury Laboratory UK and consists of 15 GRT4 VME cards and a PowerPC. The system is controlled by a PC running MIDAS software. This paper reports the current status of camera development. The pixel energy resolution has been measured to give an average of /spl sim/0.5% at 356 keV using a NIM module and /spl sim/2% using a simple digital algorithm. In addition, a centroiding algorithm that takes into consideration the induced charge from the surrounding pixels, is being implemented to improve the intrinsic spatial resolution of the camera, which is restricted by the size of the pixel (4 mm), to a target value of /spl sim/1mm; so far a X-Y position sensitivity of 2 mm has been achieved. The depth of interaction can be provided by analysis of the pulse rise time, theoretical predictions anticipate a value of the order of 0.5 mm. Currently these parameters are determined offline using simple algorithms, but it is the intention to develop the algorithms and then implement them on the FPGAs available on the GRT4 cards for online analysis.