A concurrent test architecture for massively parallel computers and its error detection capability

Presents new principles for online monitoring in the context of multiprocessors (especially massively parallel processors) and then focuses on the effect of the aliasing probability on the error detection process. In the proposed test architecture, concurrent testing (or online monitoring) at the system level is accomplished by enforcing the run-time testing of the data and control dependences of the algorithm currently being executed on the parallel computer. In order to help in this process, each message contains both source and destination addresses. At each message source, the sequence of destination addresses of the outgoing messages is compressed on a block basis. At the same time, at each destination, the sequence of source addresses of all incoming messages is compressed, also on a block basis. Concurrent compression of the instructions executed by the PEs is also possible. As a result of this procedure, an image of the data dependences and of the control flow of the currently running algorithm is created. This image is compared, at the end of each computational block, with a reference image created at compilation time. The main results of this work are in proposing new principles for the online system-level testing of multiprocessor systems, based on signaturing and monitoring the data dependences together with the control dependences, and in providing an analytical model and analysis for the address compression process used for monitoring the data routing process. >

Traditional firewalls have the ability to allow or block traffic based on source address as well as destination address and port number. Our original ROFL scheme implements firewalling by layering it on top of routing; however, the original proposal focused just on destination address and port number. Doing route selection based in part on source addresses is a form of policy routing, which has started to receive increased amounts of attention. In this paper, we extend the original ROFL (ROuting as the Firewall Layer) scheme by including source prefix constraints in route announcement. We present algorithms for route propagation and packet forwarding, and demonstrate the correctness of these algorithms using rigorous proofs. The new scheme not only accomplishes the complete set of filtering functionality provided by traditional firewalls, but also introduces a new direction for policy routing.

Design For Test (DFT) of 3D stacked integrated circuits based on Through Silicon Vias (TSVs) is one of the hot topics in the field of test of integrated circuits. This is due to the hard test accessibility (especially for upper dies) and to the high complexity where each die can embed hundreds of IPs. In this paper we propose a DFT architecture based on IEEE P1687 to enable the test of 3D stacked ICs. The proposed test architecture allows the test at all 3D fabrication levels: pre-, mid-, and postbond levels. We present a test pattern retargeting flow using IEEE P1687 languages ICL (Instrument Connectivity Language) and PDL (Procedural Description Language), which allows easy retargeting from 2D (die-level) to 3D (stack-level). Compared to IEEE 1149.1 based 3D test architecture, our proposed 3D test architecture is more flexible and enhances test concurrency without an additional area cost.

Test power consumption is becoming a major concern in low power integrated circuits(ICs). This paper presents a revised low power compression architecture for scan test. In this paper, the variance in power consumption is used to select test pattern during scan test, and a low power feedback MUX is added to the scan chains. Simulation results by mathematical methods show that the proposed test architecture is promising in reduction of power consumption.

Previous studies showed that mindfulness training and emotional stability had an impact on neural correlates of error processing. However, the impact of both trait mindfulness and emotional stability on error detection processes were not simultaneously investigated, although one could assume that there are interacting effects of the traits. We examined the individual variations of a component of the event-related potential (ERP), the error negativity (Ne/ERN), and behavioral data related to the two traits in a modified Simon task combined with an error detection task. Accounting for the positive relationship of mindfulness and emotional stability, our analyses revealed two opposing effects: a significant difference between the Ne/ERN amplitudes from detected and undetected errors was found for highly mindful participants as well as for participants with low emotional stability. These results suggest that the early error process for highly mindful participants already includes a distinction between aware and unaware errors. Moreover, low emotionally stable participants also showed higher Ne/ERN amplitudes after their aware errors than after their unaware errors, while there was no differentiation in amplitude regarding error awareness for highly emotionally stable participants. Future research should take emotional stability into account when reporting on trait mindfulness, because of possible opposing effects on performance monitoring.

Cyclic Redundancy Check (CRC) is a widely used error detection code in digital communication systems to detect errors in data transmitted between transmitter and receiver. With the development of Internet-of-Things (IoT) technology, where many devices communicate wirelessly, the application of error detection codes such as CRC is essential to obtain reliable communication. The computation of CRC can be implemented in hardware using a linear feedback shift register (LFSR) or in software with shift and bitwise exclusive OR (XOR) operations for polynomial division. Due to the frequent use of CRC in wireless communication for IoT, research for the design and implementation of CRC continues to this day. This study aims to design and implement the encoder and decoder of CRC-8 with generator polynomial 0x07 on IoT devices. Two algorithms for computing the CRC, namely bitwise computation using LFSR and another one using lookup tables, are implemented on the Arduino Uno R3 board. Two Arduino boards connected in serial were used to verify the encoder and decoder implementation in the data transmission and error detection process. The experiment results showed that the encoder could correctly calculate the CRC value from the input data. Furthermore, the computation using lookup tables takes about four times faster than the bitwise method but requires more memory. In contrast, the bitwise computation method requires less memory but slower computation time. When testing using input data of 128 characters, the bitwise-based encoder requires a computation time of 2.37 milliseconds, while the lookup table-based encoder utilizing a lookup table requires a computation time of 0.5 milliseconds. In the error detection test, the results demonstrated that the receiver could detect errors in the transmitted data with a percentage of 100%.

This paper proposes a test architecture aimed at reducing test time of distributed small embedded SRAMs (e-SRAMs). This architecture improves the one proposed in (W. B. Jone et al, Proc. 17th IEEE VLSI Test Symp., p.246- 251, 1999 and also IEEE Transact. VLSI Syst., vol.10, no.4, p.512-515, 2002). The improvements are mainly two-fold. On one hand, the testing of time-consuming data retention faults (DRFs), that is neglected by the previously proposed test architecture, is now considered and performed via a DFT technique referred to as the no write recovery test mode (XWRTM). On the other hand, a parallel local response analyzer (LRA), instead of a serial response analyzer, is used to reduce the test time of these distributed small e-SRAMs. Results from our evaluations show that the proposed test architecture can achieve a better defect coverage and test time compared to those obtained previously, with a negligible area cost.

Concurrent Error Detection (CED) methods are commonly employed to provide some level of error detection capability at the cost of some area and power overhead. In many applications, however, the error detection capability must be reconfigured dynamically, in order to adapt to the available power budget, criticality of the processed data, a thermal-safe schedule, etc. In this work, we propose a reconfigurable duplication-based CED infrastructure for logic circuits. The key idea is to enable/disable the operation of the duplicate circuit according to a set of control conditions. When CED is disabled, the inputs to the duplicate circuit retain their previous values (i.e., reduction in power dissipation via elimination of switching activity), yet errors are not detected (i.e., reduction in CED coverage). Experimental results using judicious and random selection of control conditions yield the same end-result; power dissipation is commensurate with CED coverage. Therefore, LFSR structures can be used to easily generate and reconfigure conditions, enabling their dynamic adjustment to adapt to the power constraints of the system.

The subjective experience of committed errors and the Discrepancy-Attribution hypothesis

IPv6 specifies the Fragment Header, which is employed for the fragmentation and reassembly mechanisms. The Fragment Header contains an field that, together with the IPv6 Source Address and the IPv6 Destination Address of a packet, identifies fragments that correspond to the same original datagram, such that they can be reassembled together by the receiving host. The only requirement for setting the Identification field is that the corresponding value must be different than that employed for any other fragmented datagram sent recently with the same Source Address and Destination Address. Some implementations use a simple global counter for setting the Identification field, thus leading to predictable Identification values. This document analyzes the security implications of predictable Identification values, and provides implementation guidance for setting the Identification field of the Fragment Header, such that the aforementioned security implications are mitigated.

Traditional networks make routing decisions based only on the destination address. This dramatically limits the number of ser-vices that a network can provide. However, in some of them, the demand for more flexible routing protocols has increased. For example, home and enterprise networks, as well as datacenters, need to support multi-homing and/or role-based access control. This is where two-dimensional forwarding tables step in. In this approach, routing decisions are based on the destination and the source addresses. However, this will increase the lookup time and make the memory use skyrocket if implemented carelessly. In this paper, we evaluate and compare different designs to find the best way to tackle this problem.KeywordsCommon PartTraffic ClassSource AddressDestination AddressIPv6 AddressThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Enhanced Internet security by a distributed traffic control service based on traffic ownership

Gamma interconnection network is a fault-tolerant MIN with multipath characteristics. Even though the gamma interconnection network has a multipath between every source and every destination, it has the critical flaw of acting as a single path MIN when the source address and destination address are the same. Hence, it is important to modify such a prominent candidate so as to provide multiple paths in every case, several modifications have been suggested by the researchers in the literature. One such modification is fascinating as it provides multiple paths for every case at a reduced cost. At the input and output stages, multiplexers and demultiplexers are used to do this. The system is referred to as Gamma-Minus MIN. This chapter includes further performance characteristics with the reliability assessment of Gamma.Minus MIN

A method is proposed that enables a shared single server to provide secure, customised services to multiple closed networks by using a new network address translation (NAT) function called root-side NAT. This method promises to overcome two problems involved in using agent technology in providing advanced communications services to mobile computers. Due to the shortage of global IP addresses, we are forced to dynamically assign a global address to a host at connection set-up time, or to statically assign a local address to a host. The former has a problem that a connection cannot be initiated from a server to a mobile host. The latter has a problem of duplicate addresses among closed networks, when a single server on the Internet provides secure, customized services to multiple closed networks. Our proposed method is basically based on the static assignment of local addresses. Each of multiple closed networks is connected to a server's network through a PPP (point-to-point protocol) connection. The address duplication problem is solved by translation of IP addresses using not only the IP addresses of a packet (both the source address and the destination address) but also a PPP connection identifier through which the closed network is connected to a server. This enables the server on the Internet to provide a common service such as a ticket service to multiple closed networks.

Error correction coding, channel coding, also known as error control coding, is to add some redundant code elements, or check code elements, to form a correlated sequence of code elements—code words and to use the correlation property between code elements to detect and correct errors when decoding. Different error correction coding schemes have different error detection and correction capabilities. This paper designs a combination of parity check and cyclic redundancy check (CRC) to improve the error detection and correction capabilities with minimum cost, so that the system can transmit information more efficiently while also having high transmission reliability.