A multi-mode power amplifier for enhanced PAE in back-off operation with load insensitive architecture

Based on an analog-gain control bias circuit (AGBC), a dynamic and fixed bias-controlled InGaP/GaAs HBT MMIC power amplifier module (PAM) is designed for code-division multiple-access (CDMA) and advanced mobile-phone service (AMPS) handset applications. The proposed AGBC effectively improves the power-added efficiency (PAE) of a power amplifier (PA) over a wide range of output power while satisfying the CDMA/AMPS linearity requirements. The PA gain slope with respect to AGBC mode-control voltage is about 12 dB/V. The measured average current of this AGBC PA is reduced by 64% compared to a standard PA. The AGBC PA exhibits a 28 dB power gain, a 45% PAE, and a -49 dBc adjacent channel power ratio (ACPR) at 28 dBm output power with a fixed mode-control voltage.

This paper describes a new power combining and outphasing system that provides both high efficiency and linear output control. Whereas conventional outphasing systems utilize two power amplifiers, the system introduced here combines power from four or more amplifiers. The proposed technique overcomes the loss and reactive loading problems of previous outphasing systems. It provides ideally lossless power combining, along with resistive loading of the individual power amplifiers over a very wide output power range. A conceptual development illustrating the operating principles of the system is provided, along with a representative design, detailed analysis, and supporting simulations. The relation of the proposed technique to multi-level resistance compression is also described. It is anticipated that the new power combining and outphasing modulation approach will find widespread use in applications where both high linearity and high efficiency are desired.

A nonlinear capacitance-compensation technique is developed to help improve the linearity of CMOS class-AB power amplifiers. The method involves placing a PMOS device alongside the NMOS device that works as the amplifying unit, such that the overall capacitance seen at the amplifier input is a constant, thus improving linearity. The technique is developed with the help of computer simulations and Volterra analysis. A prototype two-stage amplifier employing the scheme is fabricated using a 0.5-/spl mu/m CMOS process, and the measurements show that an improvement of approximately 8 dB in both two-tone intermodulation distortion (IM3) and adjacent-channel leakage power (ACP1) is obtained for a wide range of output power. The linearized amplifier exhibits an ACP1 of -35 dBc at the designed output power of 24 dBm, with a power-added efficiency of 29% and a gain of 23.9 dB, demonstrating the potential utility of the design approach for 3GPP WCDMA applications.

This paper proposes a half bridge CLL resonant DC-DC converter for wide output power range applications. This topology can achieve zero-voltage switching at entire load and zero-current switching for output rectifiers. The characteristics of the CLL resonant DC-DC converter are analyzed firstly. Then the design considerations for CLL resonant DC-DC converters based on wide output power range are introduced. An 150W CLL resonant converter prototype is built to verify the circuit performance with good performances on flat efficiency, narrow switching frequency range for wide output power range application at both 75V & 150V output voltage from 10% output current to 100 % output current.

In the field of power conversion for telecommunication equipment, ISDN involves various problems. One of them is to achieve the required efficiency of the DC/DC converter used to supply low power terminals such as digital telephones connected to the "S" bus. SAT has developped such a converter to equip digital telephone terminals designed for RENAN (the French experimental digital network). To fulfil the requirement of high efficiency in a wide range of output power and specially at very low output power, this converter works in two different modes : - free running frequency with fixed pulse-width for low power output corresponding to the stand by state of the terminal - fixed frequency PWM for higher output power corresponding to active states of the terminal. The control circuitry is achieved by simple low cost low power components.

During the last years, several attempts have been carried out to provide clean energy storage as an alternative to overcome the energy demand. Vanadium redox flow batteries (VRFBs) appear as a suitable device that converts the chemical energy present in the electrolyte into electrical energy in a noiseless and clean manner. In the mentioned device, the electrolyte is polarized by using renewable energy, and later the stored energy is used in several applications from mobile to stationary scenarios. There are two fundamental design parameters to be considered in the sizing of a VRFB: the state of charge (SoC), and the electrolyte volume. The mentioned parameters are related to two independent parameters of great importance, the energy consumption per unit of time (power delivered by the device), and the amount of energy that can be stored in the system (energy capacity).The purpose of the current study is, based on collected data and theoretical approximations, analyze the SoC and the required electrolyte volume for several applications. To estimate the SoC for the different VRFB, a Nernst-modified equation is used. In this case, the number of cells was a key part of achieving the desired results. A correction factor (λ) was introduced to visualize the trend of the generated curve family in a better manner. On the other hand, to calculate the volume of electrolyte, an equation derived from the definition of electric charge is implemented. Similarly, due to the power applications range covering the study, a correction factor (γ) was also introduced. Considering the obtained results, as the correction factor increases the load state in the system will tend to present higher values of open circuit voltage and nevertheless constant values of load state. Based on the energy capacity calculations, and considering common vanadium concentrations among the electrolytes, it was found that the higher the vanadium concentration the required electrolyte volume will tend to be minor. In addition, on a large scale, there is a greater convergence of the required electrolyte volume to values greater than 10 000 m3. Figure 1. Trend of the open circuit voltage (OCV) when the state of charge (SoC) is increasing. Due to the wide range of output power analyzed in the current study, all the OCV presented values have been determined by using a correction factor (λ). Figure 1

Gyrotrons operating in the millimeter and submillimeter wavelength ranges are the promising sources for applications that are requiring good spectral characteristics and a wide range of output power. We report the precise measurement results of gyrotron spectra. Experiments were conducted using a 140-GHz long-pulse gyrotron that is developed for the dynamic nuclear polarization/nuclear-magnetic-resonance spectroscopy at the Massachusetts Institute of Technology. Transient downshift of the frequency by 12 MHz with a time constant of 3 s was observed. After reaching equilibrium, the frequency was maintained within 1 ppm for over 20 s. The coefficient of the frequency change with cavity temperature was -2.0 MHz/K, which shows that fine tuning of the gyrotron frequency is plausible by cavity-temperature control. Frequency pulling by the beam current was observed, but it was shown to be masked by the downward shift of the gyrotron frequency with temperature. The linewidth was measured to be much less than 1 MHz at 60 dB relative to the carrier power [in decibels relative to carrier (dBc)] and 4.3 MHz at 75 dBc, which is the largest dynamic range to date for the measurement of gyrotron linewidth to our knowledge.

The capability of a power plant to operate at a wide range of output power is essential for initial commissioning and normal maintenance. Critical physics issues related to operating a tokamak fusion reactor at fractions of its rated power are explored, and methods for power control are identified. Analysis is carried out with a steady-state, profile-dependent, zero-dimensional power balance model of the plasma, in which several empirical transport scalings appropriate to tokamaks are used. It is found that reactor operation depends strongly on the confinement model, the plasma beta limit, and the effect of alpha power on transport. Parametric calculations indicate that density, auxiliary heating power, and an effective external confinement control mechanism are the key control elements, and burn control is required in most cases. Transition between power plateaus is facilitated by operating in the hybrid transformer mode. In general, the impact of fractional power operation on full-power reactor designs appears to be small.

This paper focuses on a systematical and in-depth analysis of the reactive power and soft-switching regions of Dual Active Bridge (DAB) converters with dual-phase-shift (DPS) control to achieve high efficiency in a wide operating range. The key features of the DPS operating modes are characterized and verified by analytical calculation and experimental tests. The mathematical expressions of the reactive power are derived and the reductions of the reactive power are illustrated with respect to a wide range of output power and voltage conversion ratios. The ZVS soft-switching boundary of the DPS is presented and one more leg with ZVS capability is achieved compared with the CPS control. With the selection of the optimal operating mode, the optimal phase-shift pair is determined by performance indices, which include the minimum peak or rms inductor current. All of the theoretical analysis and optimizations are verified by experimental tests. The experimental results with the DPS demonstrate the efficiency improvement for different load conditions and voltage conversion ratios.

A novel zero current soft-switching (ZCS)-PWM cell-assisted asymmetrical half-bridge (AHB) DC-DC converter topology with a high frequency (HF) link is proposed in this paper. The newly-proposed DC-DC converter consists of a PWM-controlled single-ended half-bridge HF inverter and a center-tapped rectifier linked with a HF transformer. In order to attain the wide range of ZCS commutation in the primary-side HF inverter, the active edge resonant snubber cell composed of a switched capacitor and a lossless inductor is adopted in the half-bridge leg, providing ZCS commutation for a wide range of output power under constant switching frequency. The operation characteristics of the DC-DC converter proposed here are described, and its feasibility data is demonstrated and evaluated with simulation and experimental results.

Main task of power semiconductor converter is transfer of electrical energy from its input to the output and to the load. This energy flow is provided by control of the switching process of one or more semiconductor devices. Based on converter application it is necessary to choose correct control algorithm for selected switching frequency of converter. Algorithm itself has to be utilized with suitable hardware platform, whereby through the set of instructions the turn on and turn of control pulses are generated. Control system also has to secure other important functions for secondary processes. Nowadays a huge number of converter topologies exists, whereby each type should be suited for different conditions of use. For example uninterruptible power supply must generate constant output voltage with constant frequency and constant amplitude for wide range of output power. Converters for electric drive applications have to control their speed through generation of three phase voltage system with configurable amplitude and speed. From mentioned above it is clear to say that for each topology of power converter, the different type of control modulation (PWM Pulse Width Modulation, PSM Phase Shift Modulation, FM Frequency Modulation) and different structure of regulator has to be used. Therefore selection of suitable control system depends on number of various factors, which are output power of converter, type of switching devices, type of load, possibility of hardware implementation and ways of switching. In the field of DC/DC converters for switching power supplies, the main focus is on implementation of digital control, which means use of microcontrollers or DSP with implemented control algorithms and functions for communication with user as well. Analog control systems are well known and its design procedure is mastered, so it is easy to convert analog (continuous) controller into discrete and consequently implementing in microcontroller and DSP. But this approach ignore sample and hold effect of A/D converter and computing time of microprocessor. For proper discrete controller design, the method named direct digital design can be used. This method uses transfer function of converter in discrete form, including effect of sampling and computation delay. For controller design purposes, transfer function of converter is necessary. This transfer function is based on model of power stage of controller. For PWM converters such as buck, boost, etc. the averaging method is widely used, but for new resonant topologies such as LLC converter, with this averaging method, the control to output transfer function cannot be used. In this chapter, new simulation based method for obtaining the transfer function of converter is discussed. This method uses MATLAB and OrCad PSPICE environments for

This paper presents implementation issues of a digital control system applied to a power factor correction (PFC) boost converter rated to a wide range of output power, operating in mixed conduction mode (MCM). The digital control system comprises an input current controller and an output voltage controller. The current controller is formed by two predictive model-based control laws, while the output voltage is regulated through a proportional-integral controller. The implementation requirements of this control system and the executed programming routines, highlighting the inductor current sampling process in different conduction modes are discussed. Experimental results applying a low cost microcontroller are shown to validate the operation of the current and voltage controllers.

This letter reports an extended GaN HEMT Doherty power amplifier (DPA). For high efficiency over a wide output power range, the DPA is designed using two cells with unequal saturation power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ). A cell with lower P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> is used as the carrier cell. For experimental validations, the carrier and peaking cells are designed and implemented with 25 W GaN HEMTs at wide-band code division multiple access (WCDMA) of 2.14 GHz, and then show the P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> of 41.3 dBm and 43.6 dBm, respectively. For the proposed DPA, the single-tone results show the power-added efficiency (PAE) of 50% at an output power of 37.3 dBm (9 dB back-off power from P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ). For a one-carrier WCDMA signal, the PAE of 47.9% with an adjacent channel leakage ratio of -35.8 dBc is obtained at 37.3 dBm, which is 7.9% improvement compared to the conventional DPA. The PAE of 40% is maintained over an 11.4 dB back-off power.

This brief presents a three-way Doherty power amplifier (DPA) with a symmetric structure in terms of the output power capacities between the carrier and peaking amplifiers for high efficiency and linearity. Based on the analysis for the efficiency peak at the output power back-off, a symmetric structure was adopted to have higher overall efficiency for the modulated signal. Through the optimized bias condition for the two peaking amplifiers, the proposed three-way DPA can be linearized in the wide output power range. To validate the proposed scheme, a three-way DPA was designed and implemented using a 60 W GaN-HEMT for the carrier amplifier and two 30 W GaN-HEMTs for the peaking amplifiers. Using a 2.14 GHz long-term evolution downlink signal with a peak-to-average power ratio of 6.5 dB, the implemented symmetric three-way DPA exhibited a drain efficiency (DE) of 33.7% and an ACLR of -38 dBc at an average output power of 41.4 dBm. Compared to the condition with the same bias for the peaking amplifiers, the DE and average output power were improved by 8.0% and 2.4 dB for the given ACLR of -38 dBc, respectively.

This paper reports the advanced design of an extended GaN HEMT Doherty power amplifier (DPA). For high efficiency over a wide output power range, the DPA is designed using two cells with uneven saturation power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ). A cell with lower P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> is used as the carrier cell. For experimental validations, the carrier and peaking cells are designed and implemented with 25-W GaN HEMTs at world interpretability for microwave access (WiMAX) band of 2.6 GHz, and then show the P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> of 40.9 dBm and 43.8 dBm, respectively. For the proposed DPA, the continuous wave results show the power-added efficiency (PAE) of 37.5% at an output power of 36 dBm (10-dB back-off power from P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ). For a WiMAX signal, the PAE of 36.9% with an relative constellation error (RCE) of -31 dB is obtained at 36 dBm, which is 7.8% improvement compared to the conventional DPA.