A New Digital Predictive Predistorter for Behavioral Power Amplifier Linearization

This paper presents a hardware implementation of a digital predistorter (DPD) for linearizing RF power amplifiers (PAs) for wideband applications. The proposed predistortion linearizer is based on a nonlinear auto-regressive moving average (NARMA) structure, which can be derived from the NARMA PA behavioral model and then mapped into a set of scalable lookup tables (LUTs). The linearizer takes advantage of its recursive nature to relax the LUT count needed to compensate memory effects in PAs. Experimental support is provided by the implementation of the proposed NARMA DPD in a field-programmable gate-array device to linearize a 170-W peak power PA, validating the recursive DPD NARMA structure for W-CDMA signals and flexible transmission bandwidth scenarios. To the best of the authors' knowledge, it is the first time that a recursive structure is experimentally validated for DPD purposes. In addition to the results on PA efficiency and linearity, this paper addresses many practical implementation issues related to the use of FPGA in DPD applications, giving an original insight on actual prototyping scenarios. Finally, this study discusses the possibility of further enhancing the overall efficiency by degrading the PA operation mode, provided that DPD may be unavoidable due to the impact of memory effects.

This paper describes an adaptive digital predistorter (ADP) for RF power amplifier (PA) linearization using an adaptive neuro-fuzzy inference system (ANFIS). The ANFIS predistorter (PD) employs the advantage of real-time modeling of the PA's responses in determining the PD's functions. The amplitude and phase corrections for the PD are represented in an easy-to-understand fuzzy if-then rule, while the parameters involved in the fuzzy representation are trained using neural networks algorithms, namely gradient-descent and least squares estimate (LSE). Experimental results show that a 26.3-dB improvement in linearity for a two-tone signal is obtained, while a distorted WCDMA signal is suppressed by at least 12 dB. The adaptability of the ANFIS PD to instantaneous variation in PA responses through time is also demonstrated, and results show that the ANFIS PD is capable of adapting to simulated environmental changes, which is a topic often omitted by researchers in this area. Further testing demonstrated that the tuning parameters involved in the training could be reduced by more than half for a fairly nonlinear PA without significantly degrading the suppression capability.

Digital predistortion (DPD), based on complex-valued memory polynomials (MP), is established as an efficient method for power amplifier (PA) linearization. The DPD facilitates compliance of the telecommunication infrastructure to strict standard specifications (transmit spectrum mask (TSM), error vector magnitude (EVM), bit error rate (BER), [Formula: see text]) by making PA more linear, while at the same time reduces the running cost of the wireless infrastructure (at both Base Transceiver Station (BTS) and User Equipment (UE) sides) by making PA more power efficient. Even when DPD is utilized, signals with high peak-to-average power ratio (PAPR) produce out-of-band PA spectrum emission due to intermodulation products affecting all above-mentioned critical standard specified parameters. The novelty proposed in this paper is as follows. PA is restricted to operate within “reasonably above” PA linear region using PAPR reduction technique. The residual nonlinearity is taken care of by DPD. The combination of DPD and PAPR PA linearization methods is implemented on software-defined radio board. The necessary steps for efficient PA linearization are presented, compensating both out-of-band and in-band signal distortions. We achieved EVM = 2.0%, ACPR [Formula: see text]50[Formula: see text]dBc, at 10[Formula: see text]W LTE modulated PA output, antenna point and PA output power of 39.5[Formula: see text]dBm.

An adaptive digital predistortion (PD) technique is proposed for linearization of power amplifiers (PAs) in multiple-input multiple-output (MIMO) transmitters. Instead of constructing a separate feedback path at each PA, we propose a PD technique based on a combined feedback, which adds all the PAs' outputs to form a single feedback. We develop an algorithm for finding the multiple PA characteristics jointly from the combined feedback. The PD parameters are calculated from the identified PA characteristics. Although the proposed method requires more computations for PA identification than the conventional method, its hardware implementation is much simpler and can overcome the crosstalk problem of a radio frequency (RF) selector, which is necessary for multiple feedback selection. The simulation results show that, despite its simple structure, the linearization performance of the proposed method is almost the same as the separate multiple feedback method.

In this paper, we present a low-power high-performance digital predistorter (DPD) for the linearization of wideband RF power amplifiers (PAs). It is based on the novel FIR memory polynomial (FIR-MP) predistorter model, which significantly augments the performance of the conventional memory polynomial predistorter with the use of complex baseband digital FIR filter prior to the memory polynomial. The adjacent channel leakage ratio (ACLR) performance comparison between the conventional MP and the proposed FIR-MP is done based on simulations with multi-carrier modulated signals of 20 and 80 MHz bandwidths. The PA models used for the simulations are extracted from the measurements of a commercial $$1\,\hbox {W}$$ GaAs HBT PA. At the ideal system-level simulations, the improvements in ACLR over the conventional MP are 7.2 and 15.6 dB, respectively, for 20 and 80 MHz signals. The choice of selection of various parameters of the predistorter along with the subsequent digital-to-analog converter (DAC) is presented. The impact of fixed-point representation is assessed using ACLR metrics, which shows that a wordlength of 14 bits is sufficient to obtain ACLR beyond $$45\,\hbox {dBc}$$ with a margin of $$10\,\hbox {dB}$$ . The proposed predistorter is synthesized in $$28\,\hbox {nm}$$ fully-depleted silicon-on-insulator (FDSOI) CMOS process. It is shown that with a fraction of the power and die area of that of the MP a huge improvement in ACLR is attained. With an overall power consumption of 8.2 and 88.8 mW, respectively, for 20 and 80 MHz signals, the FIR-MP DPD proves to be a suitable candidate for small-cell base station PA linearization.

A platform of high accuracy and reliability is crucial for power amplifier (PA) designers to assess the characteristics of the PA prototype, and for the digital predistorter engineers to validate their models and algorithms. Digital processing techniques for building a test bed of high performance for PA characterization and predistortion (PD) are discussed in this article. We also proposed a novel technique to characterize the frequency responses of the vector signal generator and vector signal analyzer independently without using any other instrument. The techniques described in this article are quite useful, especially for narrowband vector transmitters and receivers, to improve their performance. These techniques were experimentally evaluated, both for characterization and PD of a class-F PA. Test results show that using such techniques can successfully build a test bed of high accuracy and wide bandwidth. © 2012 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2013.

Current radio communication systems that adopt amplitude and phase modulations demand high linearity and high efficiency. The cascade connection between digital baseband pre-distorter (DPD) and power amplifier (PA) can be a cost-effective solution to guarantee the required linearity without compromising the efficiency. In the design of a DPD for a single band PA, direct learning can be used to extract the pre-inverse parameters or, alternatively, indirect learning can be employed by exchanging the position of the system during the identification procedure to avoid the necessity of a PA model within a closed-loop process. The performance of direct learning is substantially dependent on the accuracy of the behavioral model that replaces the PA. Furthermore, in a practical environment where only an approximation to the inverse is achieved, the linearization capability of the indirect learning is affected by shifting the post-inverse placed after the PA to a pre-inverse located before the PA. For concurrent dual-band PAs, an additional advantage of the indirect approach is that the post-inverse identifications for each band are completely independent of each other. In an authors’ previous work, a comparative analysis between the two learning architectures applied to the linearization of concurrent dual-band PAs was performed based on DPDs modeled by polynomials with memory. This work contributions are the extension of such comparative analysis to DPDs modeled by artificial neural networks, the development of complex-valued three-layer perceptrons suitable for concurrent-dual band DPDs and the introduction of a modified indirect approach to improve the accuracy of previous direct and indirect learnings. Spectre-RF transient simulations are performed in the circuit-under-test described by a wideband 130 nm CMOS PA concurrently stimulated by 2.4 GHz Wi-Fi and 3.5 GHz LTE signals. Reported simulation results show that, in a comparison with the previous direct and indirect learnings with similar output mean powers of about 60 mW, the modified indirect approach provides a superior linearity performance. The modified indirect learning reduces the error vector magnitude (EVM) metric to 0.87% and 1.13% for Wi-Fi and LTE bands, respectively, whereas the indirect and direct learnings achieve EVM equal to or larger than 1.05% and 1.49% for Wi-Fi and LTE bands, respectively.

This paper presents an adaptive Digital Predistorter (DPD) for Power Amplifier (PA) linearization whose implementation and real time adaptation have been fully performed in a Field Programmable Gate Array (FPGA) device responsible for the co-processing tasks. The predistortion function is carried out in a Basic Predistortion Cell (BPC) containing a Look-up Table (LUT). One of the main advantages of this DPD configuration is that adaptation is performed in a hot manner and therefore, it is not necessary to switch the DPD into a training mode in order to estimate the LUT contents. Results showing the linearization capabilities of this adaptive DPD are here provided.

Recently, many papers have been published on the designs of predistortion systems for power amplifiers (PA). Most of these studies are based on computer simulations. In this work, we examine our predistorter (PD) designs on a practical microwave PA in a laboratory setup. The objective is to validate two PDs of different design approaches. The first PD is modeled using a simplicial canonical piecewise linear (SCPWL) function while the second one is modeled using a polynomial function. The former exploits the properties of the SCPWL function to develop a reduced complexity PD identification method. The latter utilizes the secant method to iteratively search for the signal at the PD output, thus parameter identification is avoided. The implementation complexity and effectiveness of the PDs are compared. The limitations of the measurement system for predistorter design is also discussed briefly

High throughput coherent optical transmitters are key components in future optical communication infrastructure. However, these transmitters are often distorted with the nonlinearity of their components. A potential approach for compensating nonlinearity is by applying digital pre-distortion methods based on the Volterra series or one of its derivatives. However, the Volterra series-based solution is complex to implement, difficult to scale, and its simplified versions may not yield the desired performance. Recently digital pre distortion solutions based on neural networks were proposed, which may benefit from the generality of neural networks and can be more easily scaled. These solutions are often based on non-standard neural network architectures which require complex neurons-based architectures or being based on indirect training approach which suffer from noise enhancement. In this article, a novel method for neural network-based pre-distortion with direct learning is proposed. The direct learning with neural network does not assume a specific transmitter model and does not suffer from noise enhancement. The method assumes standard neural network inference architecture and is applied to a coherent nonlinear optical transmitted with long-short-term memory neural network. The overall performance and complexity of the direct learning method is compared with the indirect approach and with the Volterra series-based solution, showing significant advantage in performance, especially in cases of severe nonlinearity and noise conditions.

In this paper a power amplifier (PA) linearization technique is proposed where an RF predistorter (RFPD) is used in conjunction with a linearization amplifier (LA) to achieve a more effective joint pre-distortion and post-distortion linearization. This approach is suitable for use with small cells PAs because its power and cost overhead are scalable with the power range and cost of the PA. To demonstrate the technique's linearization capability, a prototype of the linearization scheme was implemented and applied to a 6-W class AB PA with a centre frequency of 850-MHz. When stimulated with a 15-MHz bandwidth modulated signal, the PA's adjacent channel leakage ratio and error vector magnitude were improved by more than 13 dB and 5 percentage points, respectively, at peak power, and up to 18 dB and 5.2 percentage points, respectively, at power backoff with the proposed linearization scheme. Furthermore, similar linearization was achieved when the PA was driven with a 40-MHz bandwidth modulated signal.

In this paper, we propose a hybrid domain framework to model the predistorter (PD) of a power amplifier (PA). It is available for obtaining the PD not only through a PA model but also a PA circuit on ADS. Simulation results show that with predistortion, the NMSE of the linearity can reach -50 dB and the ACPR can reduce around 17dB. What's more, a processing unit is designed to work with the PD, so that the PD's coefficients can adjust to the changes of the PA adaptively, making the PA perform great linear in the transmitter system. The proposed framework is a helpful guidance for the design of circuits.

Predistortion (PD) lineariser for microwave power amplifiers (PAs) is an important topic of research. With larger and larger bandwidth as it appears today in modern WiMax standards as well as in multichannel base stations for 3GPP standards, the relatively simple nonlinear effect of a PA becomes a complex memory-including function, severely distorting the output signal. In this contribution, two digital PD algorithms are investigated for the linearisation of microwave PAs in mobile communications. The first one is an efficient and low-complexity algorithm based on a memoryless model, called the simplicial canonical piecewise linear (SCPWL) function that describes the static nonlinear characteristic of the PA. The second algorithm is more general, approximating the pre-inverse filter of a nonlinear PA iteratively using a Volterra model. The first simpler algorithm is suitable for compensation of amplitude compression and amplitude-to-phase conversion, for example, in mobile units with relatively small bandwidths. The second algorithm can be used to linearise PAs operating with larger bandwidths, thus exhibiting memory effects, for example, in multichannel base stations. A measurement testbed which includes a transmitter-receiver chain with a microwave PA is built for testing and prototyping of the proposed PD algorithms. In the testing phase, the PD algorithms are implemented using MATLAB (floating-point representation) and tested in record-and-playback mode. The iterative PD algorithm is then implemented on a Field Programmable Gate Array (FPGA) using fixed-point representation. The FPGA implementation allows the pre-inverse filter to be tested in a real-time mode. Measurement results show excellent linearisation capabilities of both the proposed algorithms in terms of adjacent channel power suppression. It is also shown that the fixed-point FPGA implementation of the iterative algorithm performs as well as the floating-point implementation.

The application of digital predistortion in base band signal is an extended method of amplifier linearization to reduce the adjacent channel interference (ACI) in those systems in which a varying envelope modulation scheme like OFDM and MQAM is used. Digital baseband predistortion is a highly cost-effective way to linearize power amplifiers (PAs), but most existing architectures assume that the PA has a memoryless nonlinearity. For wider bandwidth applications such as wideband code-division multiple access (WCDMA) or wideband orthogonal frequency-division multiplexing (W-OFDM), PA memory effects can no longer be ignored. In this paper we proposed a new technique for adaptation of digital predistorter that considers memory effects in power amplifiers. This method is a combination of two techniques, memory polynomial predistortion and slope-dependent method. This new technique is validated by using a 1.9 GHz 60W LDMOS power amplifier and various signals such as 2-carrier and 3-carrier CDMA.

Bandwidth constraints pose significant challenges to linearization of wideband RF power amplifiers (PAs) with digital predistortion (DPD). A recently proposed band-limited DPD scheme uses a band-limited modeling technique to eliminate the bandwidth constraints and reduce DPD implementation cost. However, time consuming convolution operations are involved for model extraction in this time domain data based band-limited modeling method. In this article, band-limited model extraction is formulated as a generalized least squares problem and investigated from a frequency domain perspective. A frequency domain data based model extraction method is proposed, which greatly reduces the computational complexity for extracting band-limited DPD model parameters. A 10 W GaN HEMT inverse class-F PA excited by a 20 MHz four-carrier WCDMA signal and a 40 MHz two-carrier LTE signal is tested to validate the method. Experimental results show that the computationally efficient frequency domain data based model extraction method for band-limited DPD provides as good linearization performance as the time domain data based method. © 2013 Wiley Periodicals, Inc. Int J RF and Microwave CAE 24:412–420, 2014.