A new division algorithm based on lookahead of partial-remainder (LAPR) for high-speed/low-power coding applications

Recent multi-application smart cards are equipped with powerful 32-bit RISC cores clocked at 33 MHz or even more. They are able to support a variety of public-key cryptosystems, including elliptic curve systems over prime fields GF(p) and binary fields GF(2 m ) of arbitrary order. This flexibility is achieved by implementing the cryptographic primitives in software and taking advantage of dedicated instruction set extensions along with special functional units for low-level arithmetic operations. In this paper, we present the design of a low-power multiply/accumulate (MAC) unit for efficient arithmetic in finite fields. The MAC unit combines integer arithmetic and polynomial arithmetic into a single functional unit which can be configured at run-time to serve both types of fields, GF(p) and GF(2 m ). Our experimental results show that a properly designed unified (dual-field) multiplier consumes significantly less power in polynomial mode than in integer mode.

When using built-in self-test (BIST) for testing VLSI circuits the circuit response to an input test sequence, which may consist of thousands to millions of bits, is compacted into a signature which consists of only tens of bits. Usually a linear feedback shift register (LFSR) is used for response compaction via polynomial division. The compacting function is a many-to-one function and as a result some erroneous responses may be mapped to the same signature as the good response. This is known as aliasing. In this paper we deal with the selection of a feedback polynomial for the compacting LFSR, such that an erroneous response resulting from any modeled fault is mapped to a signature that is different from that for the good response. Such LFSRs are called zero-aliasing LFSRs. Only zero-aliasing LFSRs with primitive or irreducible feedback polynomials are considered due to their suitability for BIST test pattern generation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

This paper presents a new systolic VLSI architecture for computing inverses and divisions in finite fields GF(2/sup m/) based on a variant of Euclid's algorithm. It is highly regular, modular, and thus well suited to VLSI implementation. It has O(m/sup 2/) area complexity and can produce one result per clock cycle with a latency of 8m-2 clock cycles. As compared to existing related systolic architectures with the same throughput performance, the proposed one gains a significant improvement in area complexity.

We propose a sequential test pattern decompressor enabling dynamic reseeding. It reduces dependency between the decompressor output bits during the first few clock cycles after decompressor reset. Due to this fact, a lower number of clock cycles is necessary to be performed in order to encode test patterns. We evaluated features influencing the decompression quality and the hardware overhead for different decompressor principles. According to the evaluation results, we propose a decompressor combining a combinational linear decompressor and an linear feedback shift register (LFSR) like automaton, we place the combinational decompressor on the LFSR inputs. We demonstrate that due to this arrangement the combined decompressor can be used without any phase shifter and/or state skipping ability of the LFSR. We have experimentally verified that adopting the proposed decompressor structure improves test coverage, saves the hardware resources and shortens the test application time.

To obtain satisfactory fault coverage for testing a logic circuit, linear feedback shift registers (LFSRs) have been used to generate not only the pseudorandom, but also the deterministic patterns in the scan-based built-in self-test environment. However, like other scan-based methods, the LFSR based pattern generation schemes take a long test application time to feed deterministic patterns from the LFSR into a scan chain. In this paper we derive a general relationship between the bits in the scan chain and the states of the LFSR and show that any bit to be generated by an LFSR in any future clock cycle can be pre-generated by a linear function of the current LFSR state. With this relationship, we can divide a scan chain into multiple sub-chains and use one LFSR-based multiple sequence generator to simultaneously generate all the subsequences required by the sub-chains, hence can greatly reduce the test application time for deterministic patterns. Moreover, due to the scan time reduction, test power wasted during the scan operation can also be significantly reduced.

An area-efficient bit-serial sequential polynomial basis finite field GF(2m) multiplier

Finite fields are widely applied to ECC and cryptographic area, so many of researchers interested in efficient finite field arithmetic. In particular, it is efficient to use the normal basis in hardware implementation. Using the fact that the finite field GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ) is the subfield of GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mk</sup> ) when GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mk</sup> ) has the type-I optimal normal basis, in this paper, we propose a new multiplier. Comparing the complexity of the proposed multiplier with Reyhani-Masoleh's multiplier proposed in 2006 which is faster, and has smaller number of XOR gates than the existing multipliers, the number of XOR gates of the multiplier is equal to that of ours for k=4,6 and 10, the XOR critical path delay, however, is more than that of the proposed one by 20% for k=10.

It is well-known that a class of finite fields GF(2/sup n/) using an optimal normal basis is most suitable for a hardware implementation of arithmetic in finite fields. In this paper, we introduce composite fields of some hardware-applicable properties resulting from the normal basis representation and the optimal condition. We also present a hardware architecture of the proposed composite fields including a bit-parallel multiplier.

Hadamard matrix is a square matrix where any components are -1 or +1, and where any pairs of rows are mutually orthogonal. On the other hand, Hadamard-type matrix on finite fields is a similar one, but has multi-valued components on finite fields. To be more specific, we consider n × n matrices H that have their elements on the given finite fields GF(p), and satisfy HHT = nI under modulo p, where I is an identity matrix. Any additions and multiplications should be executed under modulo p. In the authors' previous studies, some properties of Hadamard-type matrices on finite fields have been proven. For example, it has been shown that the order of a Hadamard-type matrix of odd order on GF(p) is limited to a quadratic residue of a given prime p. On the other hand, it is not clear how many and how various Hadamard-type matrices on GF(p) exist in general. In this paper, we count all possible Hadamard-type matrices on finite fields when the order n of a matrix is small. We also categorize Hadamard-type matrices into six different types when n = 3 and p = 11. In addition, we prove that for any prime p, a Hadamard-type matrix over GF(p) in each of the six types always exists if and only if the order ‘3’ is a quadratic residue of a given p.

Parallelization of scalable elliptic curve cryptosystem processors in GF(2m)

Long BCH codes are broadly used in communications and storage. BCH encoders can be implemented by linear feedback shift registers (LFSRs), and modern systems demand parallel encoders to achieve high speed. LFSRs are also used for implementing cyclic redundancy check (CRC). It was shown previously that adding the input to the least significant tap of the CRC LFSR leads to the lowest complexity in the corresponding parallel architecture derived using state transition. However, the analyses for CRC LFSRs do not hold for long BCH encoders, since the parallelism needed is much smaller than the length of the LFSR for long BCH encoders. Besides, additional clock cycles are required to pad zeros to the input in order to derive the same final state for the parities. This paper first proposes a new parallel design that allows the input to be added to any tap without sacrificing the throughput. Then the matrices involved in parallel long BCH encoders are analyzed to identify the input tap leading to minimum complexity. Besides, hardware unit sharing for matrix multiplications is enabled through analyzing the timing of the encoder. For a 32-parallel (8191, 7684) BCH encoder, our design achieves 57% higher efficiency in terms of throughput/area ratio compared to the best prior design.

We present an efficient exponentiation algorithm in a finite field GF(q n ) using a Gauss period of type (n,1). Though the Gauss period α of type (n,1) in GF(q n ) is never primitive, a computational evidence says that there always exists a sparse polynomial (especially, a trinomial) of α which is a primitive element in GF(q n ). Our idea is easily generalized to the field determined by a root of unity over GF(q) with redundant basis technique. Consequently, we find primitive elements which yield a fast exponentiation algorithm for many finite fields GF(q n ), where a Gauss period of type (n,k) exists only for larger values of k or the existing Gauss period is not primitive and has large index in the multiplicative group GF(q n )×.

Recently, pairing based cryptography has drawn a lot of attention since it is the key technology to construct identity based encryption schemes. Major operations of pairing are elliptic curve computations defined upon finite field arithmetic. Hardware implementation of large prime field operation is critical to improve the practicality of pairing based cryptography. In this paper, we present a parallel processing architecture of cryptoprocessor for optimal ate pairings over BN-curves in prime field. The proposed design contains two arithmetic processing engines to complete prime field operations in parallel. Each engine is designed by the unified Fp arithmetic unit to save hardware resources. This architecture can also be used to implement RSA and ECC cryptography schemes in parallel to satisfy industry demand. The design is implemented on a Virtex-5 FPGA device. The result shows our design consumes 10592 Slices and computes optimal-ate pairing within 283,111 clock cycles, achieving a better balance between speed and area than other designs.

Consider a maximum-length shift-register sequence generated by a primitive polynomial f over a finite field. The set of its subintervals is a linear code whose dual code is formed by all polynomials divisible by f. Since the minimum weight of dual codes is directly related to the strength of the corresponding orthogonal arrays, we can produce orthogonal arrays by studying divisibility of polynomials. Munemasa (Finite Fields Appl 4(3):252---260, 1998) uses trinomials over $${\mathbb{F}_2}$$ to construct orthogonal arrays of guaranteed strength 2 (and almost strength 3). That result was extended by Dewar et al. (Des Codes Cryptogr 45:1---17, 2007) to construct orthogonal arrays of guaranteed strength 3 by considering divisibility of trinomials by pentanomials over $${\mathbb{F}_2}$$ . Here we first simplify the requirement in Munemasa's approach that the characteristic polynomial of the sequence must be primitive: we show that the method applies even to the much broader class of polynomials with no repeated roots. Then we give characterizations of divisibility for binomials and trinomials over $${\mathbb{F}_3}$$ . Some of our results apply to any finite field $${\mathbb{F}_q}$$ with q elements.

Cyclic Redundancy Check (CRC) leverages to detect the error of digital data throughout generation, transmission, storage or processing. CRCs are widely used for being simple to execute in binary appliances, crafty to mathematical simulation as well as exclusively performance oriented at identifying generic deviation occured due to intrusion in communication channels. Commonly, hardware implementation of Cyclic Redundancy Check (CRC) computations rely on the Linear Feedback Shift Registers (LFSRs). LFSR framework processes bits serially that is one message bit per clock cycle but while considering high-speed data communications, serial implementation speed is significantly inadequate which causes delay. In this research, a hardware architecture is proposed for parallel computation. Its architecture is not polynomial dependent. After testing its functionality using ModelSim, it is implemented in Altera DE1 FPGA (Field Programmable Gate Array) board and analyzed using Quartus II, TimeQuest Timing Analyzer and Power Play Power Analyzer tools. It is found that the designed took 2771 LEs (Logical Elements), it has 102 pins and consumed 120.68 mW power. Functionality test and FPGA implementation showed that CRC was computed in single clock pulse of frequency of 23.71 MHz and its throughput is 1.656 Gbps. It can be configured for a different polynomial at any time externally. The focus of the research is to represent an efficient, better throughput along with compact systematic interpretation for parallel CRC hardware which will alleviate the flaws including the challenges of the existing CRC checker which will be prominent for next generation high speed communication.