A Novel BJT Structure Implemented Using CMOS Processes for High-Performance Analog Circuit Applications

In this paper, we have proposed a new device structure of schottky-collector bipolar charge plasma transistor (SC-BCPT) with an extended base of thickness (t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> = 25 nm). The charge plasma concept eliminates different doping requirements for emitter and base regions, as a result, simplified fabrication process and improved current gain (ß). However, extended base concept yields improved cut-off frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of the proposed device. The Hafnium and stack of TiN/HfSiOx/SOI doped with Fluorine metal electrodes were employed to induce electrons and holes concentration at the emitter and base regions, respectively. Two-dimensional TCAD simulations of the proposed device demonstrate higher current gain of 37×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> and a peak cut-off frequency of 43.04 GHz as compared to the conventional SC-BCPT.

An n-p-n bipolar transistor structure with the emitter region self-aligned to the polysilicon base contact is described. The self-alignment results in an emitter-to-base contact separation less than 0.4 µm and a collector-to-emitter area ratio about 3:1 for a two-sided base contact. This ratio can be less than 2:1 for a base contacted only on one side. The vertical doping profile can be optimized independently for high-performance and/or high-density and low-power-delay circuit applications. The technology, using recessed oxide isolation, was evaluated using 13-stage nonthreshold logic (NTL) and 11-stage merged-transition logic (MTL) ring-oscillator circuits designed with 2.5 µm design rules. For transistors with 200-nm emitter junction depth the common-emitter current gain for polysilicon emitter contact is typically 2-4 times that for Pd <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> Si emitter contact. There is no observable circuit performance degradation attributable to the polysilicon emitter contact. Typical observed per-stage delays were 190 ps at 1.3 mW and 120 ps at 2.3 mW for the NTL ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FI = FO = 1</tex> ) circuits and 1.3 ns at 0.15 mA for the MTL ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FO = 4</tex> ) circuits.

Bipolar transistor action from an amorphous carbon/silicon heterojunction emitter

A novel structure of lateral bipolar junction transistor (LBJT) on selective buried oxide (SELBOX) is proposed. A 2D numerical simulation study using MEDICI has revealed that the proposed device gives a unique performance when the SELBOX is fully covering emitter and base regions and is of the length equal to the sum of lengths of emitter and base regions. For such a placement of SELBOX, a sharp increase in maximum cutoff frequency (f T ) is obtained. Further, the breakdown voltage of the proposed device at this length of SELBOX is approximately double that of an SOI device. The study of current gain (β) has revealed that there is no degradation in β at such a placement of SELBOX and is as good as in LBJT on SOI. The proposed device is expectedly thermally efficient in comparison to LBJT on SOI device and is as cool as the bulk device.

In this paper, we have designed Bipolar junction transistor (BJT) structure for small dimensions that are (given by SCL Chandigarh) and high-frequency analysis. The material used is pure Si material no compounds such as SiGe, SiC is used. This transistor is examined by various effect of parameter variations such as doping, height, length through simulations. In this paper, we have optimized the small BJT at higher beta (β) 96.50 dB, and high- frequencies ft 8.64 GHz and fmax 21.51 GHz using pure Si material.

A novel n-p-n bipolar transistor structure with polysilicon base contacts and minimized collector-to-base junction area is described. Device data obtained for this structure show that while device parameters dependent on the device doping profile remain unaffected, a considerable improvement is obtained in device parameters dependent on the size of the collector-to-base junction area.

Resistive switching in thin HfO2 films is studied using a metal-insulator-semiconductor bipolar transistor structure. Using this structure, electron injection into the semiconductor valence band can be distinguished from injection into the conduction band. In addition, the p-n junction serves as a sensitive detector of damage induced by the switching effect. The implications of the obtained experimental results on the validity of various conduction mechanisms through the insulator are discussed.

Bipolar transistor structures can be used, instead of conventional p-n (p-i-n) junctions, to realize high-speed optical modulators and switches, which are operated by free-carrier injection. Some basic results obtained by the theoretical analysis of the structure applied to a DH X crossing are presented, with emphasis on the switching speed. It is shown that switching times can be as fast as 60 ps for the required ON-OFF optical switching, which is considerably faster than those expected for a diode structure.

The authors report a new p-n-p surface accumulation layer transistor (SALTran) on SOI, which uses the concept of surface accumulation of holes near the emitter contact to significantly improve the current gain. Using two-dimensional simulation, the performance of the proposed device has been evaluated in detail by comparing its characteristics with those of the previously published conventional p-n-p lateral bipolar transistor (LBT) structure. From the simulation results it is observed that, depending on the choice of the emitter doping and the emitter length, the proposed SALTran exhibits a current gain enhancement of around twenty times that of the compatible lateral bipolar transistor, without deteriorating the cutoff frequency. Reasons for the improved performance of the SALTran are discussed, based on these detailed simulation results.

Heterojunction bipolar transistor (HBT) structures with heavily carbon and beryllium doped base layers were grown in a conventional molecular-beam epitaxy (MBE) environment. The current gain in the carbon doped structures was reduced by enhanced bulk recombination. For a hole concentration of 5 × 1019 cm−3, the carbon concentration exceeded the hole concentration and is a likely cause of the enhanced recombination. Growth conditions were determined which minimized beryllium diffusion for HBT structures with base layers doped to 1.2 × 1020 cm−3. Lattice contractions were observed at high beryllium doping concentrations. The expected reduction in resistivity with increased beryllium base doping was obtained in the HBT structures. Using HBT structures doped with beryllium at 5 × 1019 cm−3, high-power performance was obtained at 10 GHz.

The deterministic chaos mode in a basic circuit of a radiofrequency oscillator based on a bipolar transistor structure with negative resistance have been studied in this paper. Experimental research results for parameters and characteristics of the bipolar transistor structure with negative resistance have been obtained. Chaotic dynamics of the generated oscillation has been explored. Feasibility of connecting a symmetrical dipole antenna to create a transmitter with chaotic carrier has been estimated.

A new 700 V tridimensional channel-lateral insulated-gate bipolar transistor (TC-LIGBT) structure on 1.5-μm-thin silicon on insulator (SoI) layer is presented in detail in this paper. There are numerous separated p-body cells located in the emitter region of the investigated TC-LIGBT, which can increase the efficient channel width, enhance electron injection, and attain a large current capability. By optimizing the doping of the middle doped n-type region between the adjacent p-body cells, a large current density of 568 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at VGE = 10 V, VCE = 20 V can be achieved, which has an improvement of 118% compared with the conventional SoI-LIGBT structure on the same thin SoI layer. To improve the latch-up capability, a highly doped p-buried layer has also been formed underneath the emitter region using 450-keV high-energy ion implantation. In this way, the proposed new TC-LIGBT can achieve almost the same latch-up immunity capability as with the conventional SoI-LIGBT structure.

This paper addresses the performance of SiC NPN Bipolar Junction Transistors (BJTs) at high and low temperature. A current gain of 50 at room temperature was obtained which decreases to 25 at 275 oC. A maximum current gain (β) of 111 has been reported at -86 oC. At low temperature (below -86 oC), the current gain drops rapidly because of carrier freezout effect. At room temperature, a minimum on-resistance of 7 mΩ-cm2 was obtained. This increases to 28 mΩ-cm2 at 275 oC. The on-resistance of BJTs is approximately unaffected by lowering the temperature down to -86 oC from room temperature. Below -86 oC, the on-resistance jumps up rapidly because of carrier freezeout. Electrical performance of BJTs have been fairly stable during stress measurement at high temperature (120 hours at 100 oC ) at a collector bias of 1000V (with open base) for devices with a breakdown voltage of 1200V.The devices have been stressed further at low (i.e., 6) and high gain (i.e., 15) at room temperature. Initial degradation within first hour of stress test has been reported and then degradation stabilizes out. Packaged devices were tested up to 550 oC and performed admirably well up to that temperature.

Bipolar junction transistors (BJTs) of 4H-SiC, with a low collector-emitter forward voltage drop VCE have been fabricated without base contact implantation. A comparison of BJTs on the same wafer with and without base contact implantation shows less than 10% higher VCE for the BJTs without base contact implantation. Omitting the base contact implantation eliminates high concentrations of implantation-induced defects that act as recombination centers. This is advantageous because it allows a shorter distance Wp+ between the emitter edge and the base contact, without affecting the current gain when no base contact implantation is used. The BJTs without contact implantation show a constant current gain as Wp+ was reduced from 3 to 1 mum, whereas the gain decreased by 45% for the BJTs with base contact implantation for the same reduction of Wp+. A key to the successful fabrication of low-forward-voltage-drop SiC BJTs without base contact implantation is the formation of low-resistivity Ni/Ti/Al ohmic contacts to the base. The contact resistivity on the base region (NA ap 4 times1017 cm-3) was measured with linear transmission line method structures to rhoC = 1.9 times 10-3 Omegacm2, whereas the contact resistivity with the base contact implantation was rhoC = 1.3 times 10-4 Omegacm2, both after rapid thermal processing annealing at 800degC.

Existed experiments and theories have demonstrated that the polysilicon emitter contact bipolar transistor (PET) is suitable for low-temperature operation. However, an overall theory for the current gain and the cut-off frequency of PET is still absent, particularly for the quantitative modelling at high injection levels. The paper presents the quantitative relationships between the current gain, the cut-off frequency and the collector current density at 77 K and 300 K. The main physical mechanisms for the current gain and the cut-off frequency at high injection levels are also analysed. Finally, the influence of the maximum base and emitter doping concentrations on the current gain, the base and emitter transit times in polysilicon emitter contact transistors is also analysed at low temperatures. These may provide a rational basis for the design of low-temperature bipolar transistors.