Low-Forward-Voltage-Drop 4H-SiC BJTs Without Base Contact Implantation

We investigate the electrical characteristics of 1-kV pnp SiC bipolar junction transistors (BJTs) and compare them with those of npn SiC BJTs. The base resistance, current gain, and blocking capability are characterized. It is found that the base resistance of pnp SiC BJTs is two orders of magnitude lower than that of npn SiC BJTs. However, the obtained current gains are low below unity in pnp SiC BJTs, whereas npn SiC BJTs exhibit a current gain of 14 without surface passivation. The reason for the poor current gain of pnp SiC BJTs is discussed.

SiC bipolar junction transistors (BJTs) were fabricated based on the design criterion proposed in our previous study, which quantitatively proved the importance of decreasing a base spreading resistance. To reduce the base spreading resistance,Al <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -implantation was performed in the parasitic base region. No negative influences due to the implantation damage on the current gain were confirmed when the implantation is performed sufficiently apart from the emitter mesa sidewall, the distance of which is longer than 3 μm. Since the fabricated BJTs satisfied the design criterion, clear conductivity modulation was achieved, resulting in a reduced collector-resistance, that is, 50% of the unipolar resistance. In addition, we experimentally demonstrated that the conductivity modulation in SiC BJTs could be enhanced by decreasing the base spreading resistance.

Ion implantation for selective doping of SiC is problematic due to damage generation during the process and low activation of dopants. In SiC bipolar junction transistor (BJT) the junction termination extension (JTE) can be formed without ion implantation using instead a controlled etching into the epitaxial base. This etched JTE is advantageous because it eliminates ion implantation induced damage and the need for high temperature annealing. However, the dose, which is controlled by the etched base thickness and doping concentration, plays a crucial role. In order to find the optimum parameters, device simulations of different etched base thicknesses have been performed using the software Sentaurus Device. A surface passivation layer consisting of silicon dioxide, considering interface traps and fixed trapped charge, has been included in the analysis by simulations. Moreover a comparison with measured data for fabricated SiC BJTs has been performed.

This paper addresses the performance of SiC NPN Bipolar Junction Transistors (BJTs) at high and low temperature. A current gain of 50 at room temperature was obtained which decreases to 25 at 275 oC. A maximum current gain (β) of 111 has been reported at -86 oC. At low temperature (below -86 oC), the current gain drops rapidly because of carrier freezout effect. At room temperature, a minimum on-resistance of 7 mΩ-cm2 was obtained. This increases to 28 mΩ-cm2 at 275 oC. The on-resistance of BJTs is approximately unaffected by lowering the temperature down to -86 oC from room temperature. Below -86 oC, the on-resistance jumps up rapidly because of carrier freezeout. Electrical performance of BJTs have been fairly stable during stress measurement at high temperature (120 hours at 100 oC ) at a collector bias of 1000V (with open base) for devices with a breakdown voltage of 1200V.The devices have been stressed further at low (i.e., 6) and high gain (i.e., 15) at room temperature. Initial degradation within first hour of stress test has been reported and then degradation stabilizes out. Packaged devices were tested up to 550 oC and performed admirably well up to that temperature.

Silicon carbide (SiC) semiconductor devices for high power are becoming more mature and are now commercially available as discrete devices. Schottky diodes have been on the market since a few years but also bipolar junction transistors (BJTs), JFETs and MOSFETs are now reaching the market. The interest is rapidly growing for these devices in high power and high temperature applications. The BJTs have low conduction losses, fast switching capability, operate in normally-off mode, have high radiation hardness, and can handle high power density.This paper will review the current state of the art in active switching device performance with special emphasis on BJTs. Device performance has been demonstrated over a wide temperature interval. A very important feature in high power switch applications is the low on-resistance of a device. Better material quality and epi processes suppress the amount of basal plane dislocations to avoid stacking fault formation generated during high current injection. This has long been a concern for bipolar SiC devices but several research reports and long term reliability measurements of pn-junctions show that the bipolar degradation problem can be solved by a fine-tuned epitaxial technique. A discussion on surface passivation control is included.Finally, an example of a power switching module is given also demonstrating the excellent paralleling capability of BJTs.

The stability of the electrical characteristics of SiC n-p-n bipolar junction transistors (BJTs) is investigated under long-term avalanche-mode, dc, and pulsed-current operation. There is absolutely no change in the blocking I-V characteristics after a 934-h repetitive avalanche stress test. Long-term operation of the base-emitter diode (open-collector mode) alone does not result in any degradation of the ON-state voltage drop V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</sub> or current gain β. Long-term operation in common-emitter mode results in negligible V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</sub> or β degradation, if the base plate is maintained at 25°C. A greater degradation of β results upon increasing the base-plate temperature. The same total electrical charge, if passed through the BJT as a pulsed current, instead of a dc current, results in smaller β reduction. It is also shown that the β degradation can be reversed by annealing at ≥200°C, suggesting the possibility of degradation-free operation of SiC BJTs, when operating in pulsed current mode at ≥200°C temperatures.

As one of the most attractive postsilicon power semiconductor devices, SiC bipolar junction transistor (BJT) has been studied extensively and commercialized in the past few years. However, SiC BJT has not been widely accepted in the market partially because of high driver consumption in the on-state, which is induced by a relatively large constant base current in order to ensure it is fully turned on . In this paper, a new proportional base driver with a simple circuitry is proposed in order to reduce the steady-state base driver consumption of SiC BJT. It utilizes a silicon small-signal mosfet as a variable resistor placed between the driver and the base of the SiC BJT. The collector current of the SiC BJT is measured via a Hall current sensor whose output is connected to the gate of the mosfet . When the collector current decreases, the gate voltage of the mosfet decreases and its on-state resistance increases, resulting in the decrease of the actual base driver current of the SiC BJT. The operation principle of the proposed proportional base drive technique has been verified by theoretical analysis and experimental demonstration of a 1200 V 10 A-SiC BJT-based dc–dc boost converter. Theoretical calculation, PSpice simulation, and experimental results have shown that the steady-state power consumption of the SiC BJT's proportional base driver is reduced by approximately 70% under the light load condition compared to conventional base driver with a constant base current.

Low-voltage InAsP/InAs HBT and metamorphic InAs BJT devices grown by molecular beam epitaxy

The wide bandgap (WBG) semiconductor SiC has been identified as a potential candidate for use in high power and high frequency devices due to its superior material parameters. SiC has a breakdown field almost six times higher than that of Si or GaAs resulting in a higher attainable power density. SiC has a larger thermal conductivity, 3 times that of Si and 6 times that of GaAs, translating into a smaller chip size and, therefore, more efficient systems. To date, most research on SiC RF devices has focused on majority carrier devices such as SITs and MESFETs. There are only a few reports on SiC bipolar transistors and these studies have concentrated on SiC power switching transistors. Bipolar transistors have potentially superior linearity as well as higher current handling and power density capabilities compared to the aforementioned RF devices making BJTs ideal for use in power amplifiers.

Epitaxial silicon carbide bipolar junction transistors (BJTs) for power switching applications have been designed and fabricated with a maximum breakdown voltage of 1100 V. The BJTs have high common emitter current gains with maximum values exceeding 60, a result that is attributed to design optimization of the base and emitter layers and to a high material quality obtained by a continuous epitaxial growth. Device simulations of the current gain as function of collector current have been compared with measurements. The measurements show a clear emitter-size effect that is in good agreement with simulations including surface recombination in interface states at the etched termination of the base-emitter junction. Simulations indicate an optimum emitter doping around 1middot10 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> in agreement with typical state-of-the-art BJTs

Multifunctional three-dimensional heterostructures for flexible electronics have gained significant attention due to their distinctive structural formability and superior electronic and optoelectronic properties. Nevertheless, conventional fabrication techniques have yet to be optimized for flexible substrates. In this study, a straightforward fiber laser direct writing (FLDW) process is demonstrated for the simultaneous fabrication of diodes (PN junctions) and bipolar junction transistors (BJTs) on flexible polyimide substrates, which is realized through the deposition of multifunctional p- or n-type copper oxide films (CuOx) and p- or n-type porous laser-reduced graphene oxide films (LrGO) using fiber laser ablation and deposition. The presence of both p- and n-type semiconductor films is confirmed through material characterization. The fabricated PN junctions exhibit reasonable diode rectification ratios, ranging from 20 to 220, and perform reliably under numerous operating conditions such as light-dark illumination and elevated temperatures. Furthermore, I-V curve analysis indicates that the current gain and electrical performance of printed negative-positive-negative (NPN) (or positive-negative-positive, PNP) BJTs can be tailored by adjusting the laser energy density of the FLDW process and the base gap width of the BJTs. As a proof of concept, the FLDW process is successfully employed to deposit both NPN (or PNP) BJTs composed of LrGO/CuOx heterostructures with controlled current gains. Its ease of operation, versatility, and cost-effectiveness make FLDW promising for large-scale flexible electronics fabrication.

In this paper, a novel bipolar junction transistor (BJT) structure is proposed for high matching characteristics and its performance is compared with a conventional BJT structure. Although the proposed BJT matching structure indicates a decrease of collector current density <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$J_{C}$</tex></formula> and current gain <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\beta$</tex></formula> of about 5.36% and 1.02% compared with those of the conventional BJT structure, the matching characteristics of the collector current <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$(A_{\rm IC})$</tex></formula> and the current gain <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(A_{\beta})$</tex> </formula> for the proposed structure are improved by about 31% and 24%. The improved matching characteristic of the proposed structure is believed to be due to the reduced effect of the deep n-well or the reduced current path from emitter to collector.

Radiation-induced current gain and $1/f$ noise degradations in NPN bipolar junction transistors are due to accumulation of oxide-trapped charges and interface states at the surface of the device. Based on an available model of base surface current of NPN bipolar junction transistors, a simplified model is presented with some approximations at low total dose level, which can explain the degradation mechanisms of the current gain. Based on the theory of carrier number fluctuation and the simplified model of base surface current, a $1/f$ noise model is developed, which can be used to explain the $1/f$ noise degradation induced by the radiation at low total dose level. The model suggests that the gain and $1/f$ noise degradations can be attributed to the same physical origin, and these two kinds of degradations are the result of accumulation of oxide-trapped charges and interface states. The radiations were performed in a ${\rm Co}^{60}$ source at a dose rate of 10 rad(Si)/s up to a total dose of 70 krad(Si). The degradations of the current gain and $1/f$ noise are compared, and the relationship between $1/f$ noise and the current gain is given, which accords well with the experimental results. Compared to the current gain, the $1/f$ noise parameter is more sensitive, so it may be used to evaluate the radiation resistance capability of bipolar junction transistors.

The limitation of the maximum current gain attainable in a silicon bipolar transistor is due to many factors whose main effect is to prevent the blocking of minority carrier injection in the emitter. In the paper we show that blocking of minority carrier injection in the emitter, and hence a large increase of the current gain, can be achieved with a new type of npn bipolar transistor, where the emitter is made of n-doped hydrogenated amorphous silicon (a-Si: H). It is demonstrated that the very low mobility of carriers and the large bandgap (around 1.8 eV) in amorphous silicon are the two main factors involved in the improvement of the gain. The feasability and the potential interest of the device are studied in detail on the basis of the up-to-date known electrical properties of doped a-Si: H.

This paper studies two-dimensional analysis of the surface state effect on current gain for a 4H–SiC bipolar junction transistor (BJT). Simulation results indicate the mechanism of current gain degradation, which is surface Fermi level pinning leading to a strong downward bending of the energy bands to form the channel of surface electron recombination current. The experimental results are well-matched with the simulation, which is modeled by exponential distributions of the interface state density replacing the single interface state trap. Furthermore, the simulation reveals that the oxide quality of the base emitter junction interface is very important for 4H–SiC BJT performance.