SiC bipolar transistors for RF applications

We investigate the electrical characteristics of 1-kV pnp SiC bipolar junction transistors (BJTs) and compare them with those of npn SiC BJTs. The base resistance, current gain, and blocking capability are characterized. It is found that the base resistance of pnp SiC BJTs is two orders of magnitude lower than that of npn SiC BJTs. However, the obtained current gains are low below unity in pnp SiC BJTs, whereas npn SiC BJTs exhibit a current gain of 14 without surface passivation. The reason for the poor current gain of pnp SiC BJTs is discussed.

SiC bipolar junction transistors (BJTs) were fabricated based on the design criterion proposed in our previous study, which quantitatively proved the importance of decreasing a base spreading resistance. To reduce the base spreading resistance,Al <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -implantation was performed in the parasitic base region. No negative influences due to the implantation damage on the current gain were confirmed when the implantation is performed sufficiently apart from the emitter mesa sidewall, the distance of which is longer than 3 μm. Since the fabricated BJTs satisfied the design criterion, clear conductivity modulation was achieved, resulting in a reduced collector-resistance, that is, 50% of the unipolar resistance. In addition, we experimentally demonstrated that the conductivity modulation in SiC BJTs could be enhanced by decreasing the base spreading resistance.

Bipolar junction transistors (BJTs) of 4H-SiC, with a low collector-emitter forward voltage drop VCE have been fabricated without base contact implantation. A comparison of BJTs on the same wafer with and without base contact implantation shows less than 10% higher VCE for the BJTs without base contact implantation. Omitting the base contact implantation eliminates high concentrations of implantation-induced defects that act as recombination centers. This is advantageous because it allows a shorter distance Wp+ between the emitter edge and the base contact, without affecting the current gain when no base contact implantation is used. The BJTs without contact implantation show a constant current gain as Wp+ was reduced from 3 to 1 mum, whereas the gain decreased by 45% for the BJTs with base contact implantation for the same reduction of Wp+. A key to the successful fabrication of low-forward-voltage-drop SiC BJTs without base contact implantation is the formation of low-resistivity Ni/Ti/Al ohmic contacts to the base. The contact resistivity on the base region (NA ap 4 times1017 cm-3) was measured with linear transmission line method structures to rhoC = 1.9 times 10-3 Omegacm2, whereas the contact resistivity with the base contact implantation was rhoC = 1.3 times 10-4 Omegacm2, both after rapid thermal processing annealing at 800degC.

Ion implantation for selective doping of SiC is problematic due to damage generation during the process and low activation of dopants. In SiC bipolar junction transistor (BJT) the junction termination extension (JTE) can be formed without ion implantation using instead a controlled etching into the epitaxial base. This etched JTE is advantageous because it eliminates ion implantation induced damage and the need for high temperature annealing. However, the dose, which is controlled by the etched base thickness and doping concentration, plays a crucial role. In order to find the optimum parameters, device simulations of different etched base thicknesses have been performed using the software Sentaurus Device. A surface passivation layer consisting of silicon dioxide, considering interface traps and fixed trapped charge, has been included in the analysis by simulations. Moreover a comparison with measured data for fabricated SiC BJTs has been performed.

III-Nitrides promise to offer high-frequency power amplifiers at higher power densities. This is attractive for realizing device platforms for 5G and beyond. It also enables integrating Si-based electronics to complement functionalities. However, to obtain the full potential of III-Nitrides one must operate these transistors at higher power densities, for which thermal management is crucial.Due to the continuous need for higher performance in various applications ranging from DC to W-band frequencies, semiconductor devices are pushed to higher power densities. This results in a higher junction temperature owing to the Joule heating in the channel resulting in device performance degradation and premature failure. Using devices based on wide-bandgap (WBG) semiconductors such as Gallium Nitride (GaN) and Gallium Oxide (GaOx) with a larger critical electric field and high-temperature tolerance, one could increase the power density. However, in order to increase the output power to the levels that is promised by these wide bandgap materials, junction temperature reduction through device-level cooling is critical. We are actively researching thermal management at device, circuit and packaging level using synthetic polycrystalline (PC) diamond. PC-diamond, at an appropriate grain size offers a TC is higher than any competing thermal vias with metals without interfering the electrical performance. Over the past 5 years we have demonstrated the potential of integrating diamond with GaN and recently achieving a record low diamond/GaN thermal boundary resistance (TBR) along with a relatively high diamond thermal conductivity (TC). This remarkable thermal performance was be achieved by maintaining the electrical performance, as demonstrated by the unharmed channel charge and mobility results.There are two key requirements for thermal management using heat spreading from the channel: first, a low thermal boundary resistance (TBR) between the hot spot in the channel and the heat spreader is required (in this study between GaN channel and diamond). Second, a low thermal resistance path to the heat-sink is crucial from the diamond layer which is directly proportional to diamond’s thermal conductivity (TC). In collaboration with Univ of Bristol, we have reported a TBR of ~3 m2K/GW, to date, known to be the lowest reported TBR for GaN HEMT technology. Diamond-GaN TBR depends strongly on the interface smoothness and the thickness of interfacial Si3N4 layer. A thinner Si3N4 resulted in lower TBR and allowed superior phonon coupling from the channel to the spreader. We have also measured a remarkably high TC for a 2 μm-thick diamond layer yielding over 650 W/m.K. The diamond grains are near isotropic in shape that allows excellent in-plane and cross-plane thermal conductivity. Achieving high TC within a thin film of diamond, grown heterogeneously, underscores the importance of our technique, since it reduces the residual stress when integrating with different materials that involves many thin layers like GaN/AlGaN HEMT epi-layers.β-Ga2O3 is an emerging ultra-wide bandgap material showing promises for both power and RF devices. However, the material’s low thermal conductivity poses to be a challenge for efficient power delivery (at any frequencies). PC diamond was successfully grown on (‾¯201)β-Ga2O3 using proper nucleation technique and thermal characterizations were conducted. A thermal conductivity (diamond + nucleation) and thermal boundary resistance at the diamond/β-Ga2O3 interface of 110 ± 33 W/mK and 30.2 ± 1.8 m2K/GW, respectively were measured.Our current results demonstrates a very promising roadmap for wide bandgap semiconductors via diamond integration.

As one of the most attractive postsilicon power semiconductor devices, SiC bipolar junction transistor (BJT) has been studied extensively and commercialized in the past few years. However, SiC BJT has not been widely accepted in the market partially because of high driver consumption in the on-state, which is induced by a relatively large constant base current in order to ensure it is fully turned on . In this paper, a new proportional base driver with a simple circuitry is proposed in order to reduce the steady-state base driver consumption of SiC BJT. It utilizes a silicon small-signal mosfet as a variable resistor placed between the driver and the base of the SiC BJT. The collector current of the SiC BJT is measured via a Hall current sensor whose output is connected to the gate of the mosfet . When the collector current decreases, the gate voltage of the mosfet decreases and its on-state resistance increases, resulting in the decrease of the actual base driver current of the SiC BJT. The operation principle of the proposed proportional base drive technique has been verified by theoretical analysis and experimental demonstration of a 1200 V 10 A-SiC BJT-based dc–dc boost converter. Theoretical calculation, PSpice simulation, and experimental results have shown that the steady-state power consumption of the SiC BJT's proportional base driver is reduced by approximately 70% under the light load condition compared to conventional base driver with a constant base current.

Silicon carbide (SiC) semiconductor devices for high power are becoming more mature and are now commercially available as discrete devices. Schottky diodes have been on the market since a few years but also bipolar junction transistors (BJTs), JFETs and MOSFETs are now reaching the market. The interest is rapidly growing for these devices in high power and high temperature applications. The BJTs have low conduction losses, fast switching capability, operate in normally-off mode, have high radiation hardness, and can handle high power density.This paper will review the current state of the art in active switching device performance with special emphasis on BJTs. Device performance has been demonstrated over a wide temperature interval. A very important feature in high power switch applications is the low on-resistance of a device. Better material quality and epi processes suppress the amount of basal plane dislocations to avoid stacking fault formation generated during high current injection. This has long been a concern for bipolar SiC devices but several research reports and long term reliability measurements of pn-junctions show that the bipolar degradation problem can be solved by a fine-tuned epitaxial technique. A discussion on surface passivation control is included.Finally, an example of a power switching module is given also demonstrating the excellent paralleling capability of BJTs.

A compact, high power amplifier MMIC operating at Ka/Q-band was designed and developed using TriQuint's 3MI dual-recess 0.15 /spl mu/m gate length GaAs PHEMT technology. This single-ended three-stage power amplifier, with chip size of 7.44 mm/sup 2/ (3.145 mm /spl times/ 2.367 mm), on 100 /spl mu/m GaAs substrate achieved 33 dBm (2 Watt) P/sub 1dB/ CW output power and up to 2.5 Watts saturated output power with small signal gain of 21 dB over 33-36 GHz. The RF response of this amplifier can be further extended to cover frequencies of 32 - 38 GHz. For 37 - 38 GHz, this power amplifier demonstrated 32 dBm (1.6 Watt) saturated output power and 31 dBm P/sub 1dB/ with 18 dB small signal gain. This state-of-the-art power amplifier MMIC is a smallest chip size and highest output power density from a single MMIC reported to date at Ka/Q-band.

Hexagonal boron nitride (h-BN) is widely used as a two-dimentional (2D) insulating material. Owing to its high breakdown field (8-12 MV/cm), wide band gap (5.2-5.9 eV), and thermal⋅chemical stability, h-BN is employed as a dielectric layer of 2D integrated electronic device. Unlike to other insulating materials, h-BN has an atomically flat surface free from the dangling bond at the interface. Therefore, it is less affected by trap charges and mismatch of the lattice structure. Without any complicated process, it is possible to obtain an atomically thin flake by mechanical exfoliation and is easy to apply to extremely thin electronic device application such as field effect transistor and complementary metal-oxide semiconductor. Dielectric layer of semiconductor device must maintain its insulating property in extreme condition. It is of great importance to find out the breakdown field to ensure the stability of the device. However, the atoms constituting the lattice of the insulator can be damaged by protons, heavy ions and cosmic rays. These rays make an irreversible degradation on the insulating materials, and the destruction of the lattice structure can be accompanied. It poses a critical hazard on the performance of the device in that degradation of insulator lead to lower the breakdown field of dielectric layer. Measurement of changes of the breakdown field by radiation can define the safe operating voltage range of the device. H-BN is a next-generation insulating material, but the effect of radiation on h-BN has not been fully studied. In this work, we quantitatively analyzed the damage on h-BN and effect on breakdown field from varying proton-ray irradiation conditions. We fabricated pre-patterned source/drain electrode of Ti/Au on a Si/SiO2 wafer. A thin h-BN flake was mechanically exfoliated from the high-crystalline h-BN bulk crystal. Prepared flakes were transferred to the substrate by dry transfer method. We employed atomic force microscope to measure the thickness of h-BN. H-BN flakes were proton-irradiated under varying condition of power (5MeV, 10MeV) and fluence (1×1013, 5×1013). To measure breakdown field, graphene was used as a top electrode on h-BN to creat a vertical structure. We proceeded a electrical measurement to find out the hard breakdown field of pristine and irradiated h-BN flakes respectively. Mean value of the breakdown field of pristine h-BN flakes is 10.532 MV/cm, comparable with value of reported exfoliated h-BN. Whereas the breakdown field of proton-irradiated h-BN flakes ranged from 1 to 7 MV/cm. We used density functional theory and molecular dynamics simulation to estimate the mechanism of damaging on the lattice structure of h-BN. Proton irradiation causes irreversible degradation on atomic structure of h-BN, such as interstitial or vacant defects. This triggered a sudden current jump and failure at a lower voltage. We can enable more stable operation by considering the expected breakdown field of the device under the condition of radiation. Details of our work will be discussed in the presentation.

Compact Modeling of Physical Mechanisms Present in the Weak Breakdown Regime of Advanced Si and SiGe Bipolar Transistors

A cofired hetero-laminated low-temperature cofired ceramics (LTCC) power inductor device comprising cofirable NiCuZn ferrite body and Zn2SiO4 ceramic layers was designed, manufactured, and characterized. These produced LTCC power inductors were revealed to possess excellent characteristics including high inductance of $2.0~\mu \text{H}$ , small volume of 2 $\times1.2\times0.9$ mm3 (0805 packaging standard), low resistance of $0.20~\Omega $ , large current handling capability of 430 mA, low cost, and wide operating temperature range via a combination of characterization tools. Unlike the previously reported ceramic/ferrite hetero-laminates fabrication method, the process introduced in this paper involves no extra buffer layer or mechanical pressing sinter. Instead, a conventionally standard LTCC process was used for manufacturing these power inductors. To select the NiCuZn ferrite body with simultaneous high inductance and current handling capability for targeted power inductor design, the saturation magnetization and intrinsic coercivity of a variety of NiCuZn ferrite body prepared under different compositions, additives, and sintering conditions were carefully measured via vibrating sample magnetometer and under swept superpositioned dc magnetic field. Then, the power inductors with uniform sizes were mass produced using the selected NiCuZn body and Zn2SiO4 ceramic layers. The microstructure, magnetic element interdiffusion, interior circuit position, and inductance were detailed examined utilizing scanning electron microscopy, energy-dispersive X-ray spectroscopy, industrial computerized tomography scan, and RF impedance/material analyzer.

During the last few decades, the microelectronics packaging industry has moved into the 2.5D to 3D space for increased density, functionality, and speed. Similar concepts and ideas for developing 2.5D to 3D power electronics packaging are desired to achieve even greater efficiency and power density over conventional power electronics packaging methods. Wide-band gap (WBG) semiconductors, such as SiC and GaN, have accelerated the ability to shrink the volumetric size and weight of these power conversion systems, and thus improve overall power density metrics, due to their inherent high frequency, high temperature, and high voltage capabilities. WBG power semiconductor devices, with these attributes, thus make themselves excellent candidates for more aggressive packaging, compared to Si-derived packaging, in order to not only take full advantage of the WBG device ratings, but also to achieve high power densities of the overall power conversion systems. Already different/multiple power semiconductor devices are being combined by processing them together on the same die to boost electrical performance and increase power density. It can be assumed that further levels of integration will be sought after for the next levels of packaging to enable similar gains, especially with the advent of double side solderable die. The 3D stacking of die, components, and substrates creates the question of how well will each of these perform in close proximity to each other. This work focuses on the numerical simulation and experimental measurements to predict the temperature distribution of power converters built in a stacked fashion. Thermal models of a stacked power electronic switching unit — a silicon controlled rectifier and anti-parallel diode — are modeled under the assumption of equally sized die. Temperature field maps are generated for 20W to 250W of power dissipations across the power semiconductor die. Thermal models are then compared with matching experimental setups to observe the effect of switching unit placement attached to a given substrate on the die junction temperatures for various scenarios of thermal crosstalk. Results from this work are expected to aid in the development 2.5D to 3D power electronic packaging by predicting thermal performance of stacked, ultra-dense, WBG device -based packages.

A fully integrated K-band transformer combined power amplifier was designed and fabricated in 0.18-um CMOS technology. The circuit design and layout arrangement are elaborately planned to achieve 0.2 mm2 occupation chip size with the acceptable power performance. To the best of the author's knowledge, this work has the smallest chip size among the reported 0.18-um CMOS K-band power amplifier.

There is a continuous demand for improvements in the quality of switching power devices, such as higher switching frequency, higher withstand voltage capability, larger current-handling capability, and lower conduction losses. However, for single-conduction-mechanism devices (SCRs, GTOs, BJTs, FETs), possessing all these features is probably unrealizable for physical reasons. An attractive solution appears to be double-mechanism devices, in which the features of both a minority carrier device (BJT or SCR) and a majority carrier device (MOSFET) are embedded. Both IGBTs (insulated-gate bipolar transistors) and MCTs (MOS-controlled thyristors) belong to this family of double-mechanism devices and promise to have a major impact on converter circuit signs. The authors deal with the major features of these two devices, pointing out those that are most critical to the design of power converter topologies. In particular, the two devices have been tested both in a chopper and in two resonant link converter topologies, and the experimental results are reported. >

The power amplifier which is designed by using BJT (Bipolar Junction Transistor) has a larger power consumption, hence in this research, the FET GaAs p-HEMT MMG15241H is used. The power amplifier designed in this research uses microstrip-based and works at the middle frequency of 1.27 GHz. This research yielded a power amplifier which works at the bandwidth with a range frequency of 1.265 – 1.275 GHz, a gain result of 20.02 dB, and input return loss result of -24.45 dB.