Extended Base Schottky-Collector Bipolar Charge Plasma Transistor

In this paper, a novel bipolar junction transistor (BJT) structure is proposed for high matching characteristics and its performance is compared with a conventional BJT structure. Although the proposed BJT matching structure indicates a decrease of collector current density <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$J_{C}$</tex></formula> and current gain <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\beta$</tex></formula> of about 5.36% and 1.02% compared with those of the conventional BJT structure, the matching characteristics of the collector current <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$(A_{\rm IC})$</tex></formula> and the current gain <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(A_{\beta})$</tex> </formula> for the proposed structure are improved by about 31% and 24%. The improved matching characteristic of the proposed structure is believed to be due to the reduced effect of the deep n-well or the reduced current path from emitter to collector.

A new structure for a symmetric bipolar charge-plasma transistor device with an extruded base is proposed. The charge plasma and extruded base concepts are used to increase the current gain and cutoff frequency of the proposed device, respectively. Metal contact hafnium accumulates electrons in the emitter/collector (E/C) regions and platinum accumulates holes in the base region. Using the metal contact of different work functions, the electrons and holes are accumulated in a lightly doped silicon film to create the E/C and the base regions, respectively. Two-dimensional simulations of the proposed device demonstrate that it has a higher current gain of 9 × 106 and a peak cutoff frequency (fT) of 87.3 GHz. Furthermore, the fT for different silicon film thicknesses and base widths is optimised.

Two-zone SiGe base heterojunction bipolar charge plasma transistor for next generation analog and RF applications

A novel structure of lateral bipolar junction transistor (LBJT) on selective buried oxide (SELBOX) is proposed. A 2D numerical simulation study using MEDICI has revealed that the proposed device gives a unique performance when the SELBOX is fully covering emitter and base regions and is of the length equal to the sum of lengths of emitter and base regions. For such a placement of SELBOX, a sharp increase in maximum cutoff frequency (f T ) is obtained. Further, the breakdown voltage of the proposed device at this length of SELBOX is approximately double that of an SOI device. The study of current gain (β) has revealed that there is no degradation in β at such a placement of SELBOX and is as good as in LBJT on SOI. The proposed device is expectedly thermally efficient in comparison to LBJT on SOI device and is as cool as the bulk device.

Charge plasma based devices are gaining interest due to various reasons, since these devices doesn’t require conventional ways of creating different doping regions, therefore these devices are free from various doping related issues related, as random doping fluctuations, doping activations and the requirement of high temperature annealing are absent in these devices. In this work we put forward a novel lateral pnp bipolar transistor on silicon on insulator. Metals of different work function are used to induce n and p type charge plasma on undoped silicon to have emitter, base and collector regions. The 2D simulation study has revealed that a very high current gain is achieved in the proposed device in comparison to conventional pnp transistor. The charge plasma concept is very much appropriate in surmounting the doping related issues such as diffusion or ion implantation, random doping fluctuations and high thermal budget in current nano devices.

Heterojunction bipolar transistor (HBT) structures with heavily carbon and beryllium doped base layers were grown in a conventional molecular-beam epitaxy (MBE) environment. The current gain in the carbon doped structures was reduced by enhanced bulk recombination. For a hole concentration of 5 × 1019 cm−3, the carbon concentration exceeded the hole concentration and is a likely cause of the enhanced recombination. Growth conditions were determined which minimized beryllium diffusion for HBT structures with base layers doped to 1.2 × 1020 cm−3. Lattice contractions were observed at high beryllium doping concentrations. The expected reduction in resistivity with increased beryllium base doping was obtained in the HBT structures. Using HBT structures doped with beryllium at 5 × 1019 cm−3, high-power performance was obtained at 10 GHz.

A self-aligned vertical Bipolar Charge Plasma Transistor (V-BCPT) with a buried metal layer between undoped silicon and buried oxide of the silicon-on-insulator substrate, is reported in this paper. Using two-dimensional device simulation, the electrical performance of the proposed device is evaluated in detail. Our simulation results demonstrate that the V-BCPT not only has very high current gain but also exhibits high BVCEO · fT product making it highly suitable for mixed signal high speed circuits. The proposed device structure is also suitable for realizing doping-less bipolar charge plasma transistor using compound semiconductors such as GaAs, SiC with low thermal budgets. The device is also immune to non-ideal current crowding effects cropping up at high current densities.

The authors report a new p-n-p surface accumulation layer transistor (SALTran) on SOI, which uses the concept of surface accumulation of holes near the emitter contact to significantly improve the current gain. Using two-dimensional simulation, the performance of the proposed device has been evaluated in detail by comparing its characteristics with those of the previously published conventional p-n-p lateral bipolar transistor (LBT) structure. From the simulation results it is observed that, depending on the choice of the emitter doping and the emitter length, the proposed SALTran exhibits a current gain enhancement of around twenty times that of the compatible lateral bipolar transistor, without deteriorating the cutoff frequency. Reasons for the improved performance of the SALTran are discussed, based on these detailed simulation results.

Existed experiments and theories have demonstrated that the polysilicon emitter contact bipolar transistor (PET) is suitable for low-temperature operation. However, an overall theory for the current gain and the cut-off frequency of PET is still absent, particularly for the quantitative modelling at high injection levels. The paper presents the quantitative relationships between the current gain, the cut-off frequency and the collector current density at 77 K and 300 K. The main physical mechanisms for the current gain and the cut-off frequency at high injection levels are also analysed. Finally, the influence of the maximum base and emitter doping concentrations on the current gain, the base and emitter transit times in polysilicon emitter contact transistors is also analysed at low temperatures. These may provide a rational basis for the design of low-temperature bipolar transistors.

A new 700 V tridimensional channel-lateral insulated-gate bipolar transistor (TC-LIGBT) structure on 1.5-μm-thin silicon on insulator (SoI) layer is presented in detail in this paper. There are numerous separated p-body cells located in the emitter region of the investigated TC-LIGBT, which can increase the efficient channel width, enhance electron injection, and attain a large current capability. By optimizing the doping of the middle doped n-type region between the adjacent p-body cells, a large current density of 568 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at VGE = 10 V, VCE = 20 V can be achieved, which has an improvement of 118% compared with the conventional SoI-LIGBT structure on the same thin SoI layer. To improve the latch-up capability, a highly doped p-buried layer has also been formed underneath the emitter region using 450-keV high-energy ion implantation. In this way, the proposed new TC-LIGBT can achieve almost the same latch-up immunity capability as with the conventional SoI-LIGBT structure.

Numerical simulations with a one-dimensional physical device model are used to investigate the importance of the design of the emitter and base regions of n-p-n GaAs/AlGaAs HBT structures. A structure of optimum gain and speed is determined together with limits for the variations of the aluminum gradings and doping placement. The simulations show that the edge of the base doping on the emitter side has to be controlled within a few nanometers to avoid serious degradations of the current gain and the cutoff frequency. Variation in the position of the base doping relative to the aluminum gradings is a plausible source of the spread in current gain observed in measurements of devices made by metalorganic vapor-phase epitaxy (MOVPE). It is predicted that longer emitter aluminum gradings will reduce the sensitivity to these variations together with the peak values of gain and speed. It is suggested that the grading length be chosen as a compromise between performance and uniformity depending on the accuracy of the manufacturing method and the demands of the application.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The optimization of the construction and technology of bipolar self-aligned SHF transistor structures with direct and inverted ultrathin emitter regions is carried out. The threshold amplification frequency and maximum oscillation frequency, which are 500 GHz, are shown to be reachable when using self-adjoined pseudo-lithographic masks and decreasing parasitic capacities and resistances. Methods for creating direct and inverted extremely narrow emitter regions doped with arsenic are proposed.

An n-p-n bipolar transistor structure with the emitter region self-aligned to the polysilicon base contact is described. The self-alignment results in an emitter-to-base contact separation less than 0.4 µm and a collector-to-emitter area ratio about 3:1 for a two-sided base contact. This ratio can be less than 2:1 for a base contacted only on one side. The vertical doping profile can be optimized independently for high-performance and/or high-density and low-power-delay circuit applications. The technology, using recessed oxide isolation, was evaluated using 13-stage nonthreshold logic (NTL) and 11-stage merged-transition logic (MTL) ring-oscillator circuits designed with 2.5 µm design rules. For transistors with 200-nm emitter junction depth the common-emitter current gain for polysilicon emitter contact is typically 2-4 times that for Pd <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> Si emitter contact. There is no observable circuit performance degradation attributable to the polysilicon emitter contact. Typical observed per-stage delays were 190 ps at 1.3 mW and 120 ps at 2.3 mW for the NTL ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FI = FO = 1</tex> ) circuits and 1.3 ns at 0.15 mA for the MTL ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FO = 4</tex> ) circuits.

For the first time, we have explored the effect of positive and negative interface trap charges on the dopingless device using charge plasma concept and named the proposed device as heterogeneous gate dielectric charge plasma tunnel field-effect transistor (HD-CP-TFET). The heterogeneous gate dielectric is considered to improve the ON-state current and device performance. The main intention of this work is to improve the drain current, transconductance characteristics along with linearity figure-of-merits (FOMs). A comparative analysis is done with conventional CP-TFET in the presence of interface trap charges (ITCs). From comparative results, it is found that the proposed device shows a better performance in the presence of interface trap charges. All the simulations are performed on ATLAS TCAD device simulator. The results show that the proposed device has a better tunneling current, transconductance (\(g_{\text {m}}\)), cut-off frequency (\(f_{\text {T}}\)), second-order voltage intercept point (VIP2), third-order voltage intercept point (VIP3), third-order input intercept point (IIP3), and third-order intermodulation distortion (IMD3). Thus, the proposed device (HD-CP-TFET) shows the better performance in the presence of interface trap charges and indicates that this device is suitable for low-voltage analog/RF applications.

We study the effects of recombination and generation process on the operation of bipolar junction transistor based on two-dimensional materials, and in particular, graphone. Here, we use Shockley–Read–Hall model to study these process. First, we investigate the current–voltage characteristics of a graphone p–n junction considering generation and recombination process. Then, we calculate the estimated changes in current gain, cutoff frequency, and output characteristics of a graphone bipolar junction transistor designed in a recent study.