Vertical Bipolar Charge Plasma Transistor with Buried Metal Layer

In this Letter, a novel vertical bipolar junction transistor (BJT) triggered silicon‐controlled rectifier (VBTSCR) is proposed for advanced nanoscale electrostatic discharge (ESD) protection applications. With the help of a vertical NPN transistor in floating base configuration, the new silicon‐controlled rectifier (SCR) structure achieves lower trigger voltage and better clamping capacity than the prior enhanced modified lateral SCR (EMLSCR) under the same layout footprint. The ESD characteristics are measured using the transmission line pulsing tester. Compared with that of EMLSCR, the trigger voltage of VBTSCR drops by 1 V, and the effective ESD robustness of VBTSCR has been doubled significantly. Based on these advantages, the proposed VBTSCR can provide ESD protection for the advanced 1.8/2.5 V input/output circuits more efficiently.

A new dc measurement technique that allows a direct observation of the Early effects and the base push-out effect in vertical bipolar transistors is described. The technique uses a special test structure and may be used to accurately determine the forward and reverse Early voltages used in the Gummel Poon model. The improvements provided by this method over conventionally used parameter extraction techniques are demonstrated through measurements on silicon and through two-dimensional device simulations.

Two-zone SiGe base heterojunction bipolar charge plasma transistor for next generation analog and RF applications

The silicon-based gate-controlled lateral bipolar junction transistor (BJT) is a controllable four-terminal photodetector with very high responsivity at low-light intensities. It is a hybrid device composed of a MOSFET, a lateral BJT, and a vertical BJT. Using sufficient gate bias to operate the MOS transistor in inversion mode, the photodetector allows for increasing the photocurrent gain by 106 at low light intensities when the base-emitter voltage is smaller than 0.4 V, and BJT is off. Two operation modes, with constant voltage bias between gate and emitter/source terminals and between gate and base/body terminals, allow for tuning the photoresponse from sublinear to slightly above linear, satisfying the application requirements for wide dynamic range, high-contrast, or linear imaging. MOSFETs from a standard 0.18-μm triple-well complementary-metal oxide semiconductor technology with a width to length ratio of 8 μm /2 μm and a total area of ~ 500 μm2 are used. When using this area, the responsivities are 16-20 kA/W.

To improve the value of β of a pnp-merged vertical bipolar transistor (VBT) in ‘pseudo-BiCMOS’ technology, a novel VBT design with an inversion layer-extended emitter is proposed. A high emitter injection efficiency of the forward-biased inversion layer is demonstrated in a pnp VBT fabricated in 1 µm compensated CMOS technology.

Scaling of microwave noise and small-signal parameters of InP-based Double Heterojunction Bipolar Transistors (DHBTs) with high DC current gain is presented. Three different sizes of InP/InGaAs DHBT are investigated in this work. Because of the low surface and intrinsic recombination of the InP-based DHBT with high current gain, the extrinsic parasitic effect of the device can be neglected. Thus, the microwave parameters of large size InP DHBT can be obtained by scaling the parameters of the smaller emitter size device. Good agreement was obtained between the measured and the calculated results. This scaling technique is very useful for the design of high frequency circuits using InP-based HBTs.

GaN‐based vertical transistors have demonstrated its excellent properties for high‐power and high‐frequency electronic devices. This work introduces a GaN‐based static induction transistor (SIT) which is another form of vertical GaN transistors without requiring any p‐type GaN and gate dielectrics for its operation. Processing strategy to generate the GaN SIT with a sub‐micrometer fin width involves photoresist (PR)‐assisted planarization with an understanding of dry etch parameters for the planar PR surface. The efficacy of this process is demonstrated by the device's triode‐like output characteristics with high current density (0.65 kA cm−2) and low ON resistance (1.48 mΩ cm2) at 1 V of drain voltage. In addition, the electrical properties such as current density and modulation are examined depending on the fin width of GaN SIT. The result reveals that the size reduction in the GaN SIT utilizing the sub‐micrometer fin as a channel could increase the current modulation, but it could decrease the current density because of the raised potential minima due to the depletion region overlap. It is believed that the GaN SIT demonstrating high blocking voltage and low ON resistance would present a very promising class of transistor for next‐generation high‐power and high‐frequency electronics.

Most of the semiconductor device geometries that are being experimented with for improved magnetic field sensing do not lend themselves to accurate analytical modeling. The vectorial interaction taking place between the electrical current and the magnetic field complicates the problem of solving nonlinearly coupled carried density and electrostatic potential equations. In this work, solutions to the carrier density and electrostatic potential distributions are obtained by using a finite-element technique for a structure representing lateral and vertical bipolar transistors with multiple collectors. The results presented show the effect of the magnetic field to be very nonuniformly distributed around the emitter with a heavy-concentration near the emitter edges where the Lorentz-force-driven carriers are stopped at the insulating boundaries and give rise to a magnetoconcentration in the carrier densities. Distribution of currents collected by a multitude of collectors surrounding the emitter and their sensitivity to the magnetic field are given. The vertical magnetosensitivities are found to be an order of magnitude smaller than the lateral magnetosensitivity because of the lack of such a magnetoconcentration of carriers under the emitter. The computer program developed can simulate unipolar as well as bipolar magneto-sensitive devices with any boundary geometry.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Charge plasma based devices are gaining interest due to various reasons, since these devices doesn’t require conventional ways of creating different doping regions, therefore these devices are free from various doping related issues related, as random doping fluctuations, doping activations and the requirement of high temperature annealing are absent in these devices. In this work we put forward a novel lateral pnp bipolar transistor on silicon on insulator. Metals of different work function are used to induce n and p type charge plasma on undoped silicon to have emitter, base and collector regions. The 2D simulation study has revealed that a very high current gain is achieved in the proposed device in comparison to conventional pnp transistor. The charge plasma concept is very much appropriate in surmounting the doping related issues such as diffusion or ion implantation, random doping fluctuations and high thermal budget in current nano devices.

Reducing the size of silicon devices is accompanied by an increase in the effective rate of electrons, decrease transit time and the transition to a ballistic work.Power consumption is reduced too. Formation of large integrated circuits structures onSi-homotransition reduces their frequency range and performance.Nowadaysproposed several new types of devices and technologies forming of large integrated circuits structures that based on high speeds and mobility of electrons in GaAs, and small size structures.These include, for example, the heterostructure field-effect transistors on a segmented doping, bipolar transistors with wide-emitter, transistor with soulful base, vertical ballistic transistors, devices with flat-doped barriers and hot electron transistors as element base of modern high-speed large integrated circuits.In this article we consider graded-gap technology formatting as bipolar and field-effect transistors, which are the basis of modern high-speedof large integrated circuits structures.

In this paper, we have proposed a new device structure of schottky-collector bipolar charge plasma transistor (SC-BCPT) with an extended base of thickness (t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> = 25 nm). The charge plasma concept eliminates different doping requirements for emitter and base regions, as a result, simplified fabrication process and improved current gain (ß). However, extended base concept yields improved cut-off frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of the proposed device. The Hafnium and stack of TiN/HfSiOx/SOI doped with Fluorine metal electrodes were employed to induce electrons and holes concentration at the emitter and base regions, respectively. Two-dimensional TCAD simulations of the proposed device demonstrate higher current gain of 37×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> and a peak cut-off frequency of 43.04 GHz as compared to the conventional SC-BCPT.

Strained bipolar charge plasma transistor as a high speed LIF neuron

A detailed examination of the physics of the InP based heterostructure bipolar transistors is reported. The governing drift and diffusion and Poisson's equations are solved numerically in two dimensions. The results show current gain as high as 26300 and an fT of 78.6 GHz for an InP/InGa As/InP double heterostructure. The electric field profiles from the simulation are used in an adjunct Monte Carlo procedure to assess the effects of velocity overshoot. The Monte Carlo results indicate a substantial reduction in base and collector transit times from the corresponding drift and diffusion equation (DDE) simulations.

The features of modern complementary bipolar technologies (CB-technologies) for analog applications have been analyzed and the main trends in their development are considered. Different industrial CBtechnologies are compared on the basis of two parameters of complementarity, namely the quality factor (βV A ) and Johnson’s parameter (BV CEO f T ). The p-epitaxial-planar CB-technology has been studied by the method of two-dimensional numerical simulation using the TCAD Sentaurus software for vertical n–p–n and p–n–p transistors. A careful calibration of the parameters of technological and electrophysical 2D models on the basis of test structures has shown sufficient accuracy of the used methodology for practice.

The static and dynamic performance of 600-V, n-channel, vertical insulated-gate bipolar transistors (IGBTs) at temperatures as low as 77 K has been measured and analyzed. The IGBTs demonstrate a better performance in turn-off times and maximum gate controllable current, at the expense of a slightly higher forward drop. It is shown that inherent in the IGBT is a parasitic thyristor that must be suppressed to retain gate-control operation. At 300 K, the dynamic latching current or maximum gate controllable current of the n-IGBT was 3.3 A, but it was current limiting at 5.4 A at both 195 and 77 K. Hence, by simply lowering the operating temperature, one can achieve the desirable current-limiting feature rather than encounter the often destructive latching behavior. >