A new approach for extracting base width modulation parameters in bipolar transistors

A self-aligned vertical Bipolar Charge Plasma Transistor (V-BCPT) with a buried metal layer between undoped silicon and buried oxide of the silicon-on-insulator substrate, is reported in this paper. Using two-dimensional device simulation, the electrical performance of the proposed device is evaluated in detail. Our simulation results demonstrate that the V-BCPT not only has very high current gain but also exhibits high BVCEO · fT product making it highly suitable for mixed signal high speed circuits. The proposed device structure is also suitable for realizing doping-less bipolar charge plasma transistor using compound semiconductors such as GaAs, SiC with low thermal budgets. The device is also immune to non-ideal current crowding effects cropping up at high current densities.

A comprehensive bipolar transistor model based on the Gummel–Poon model [Bell Syst. Tech. J. 49, 827 (1970)] for low-temperature circuit simulation is presented. Relevant low-temperature physics such as doping-dependent dielectric permittivity, temperature-dependent free-carrier mobility and intrinsic carrier density, and de-ionization of impurity dopants are included in the model. Consequently, the model does not require temperature fitting parameters as does the Gummel–Poon model. Comparisons of the present model with the Gummel–Poon model, with experimental data, and with simulation from a two-dimensional device simulator (pisces) are included.

The gate length and gate contour of a GaAs metal–semiconductor field effect transistor (MESFET) device play important roles in determining the small signal circuit parameters and large signal breakdown voltage behavior. GaAs MESFETs with different gate lengths and gate contours were studied by the two-dimensional (2-D) semiconductor device simulations to investigate the dependence of small signal circuit parameters and breakdown voltage on gate length and gate contour. The results show that gate length affects small-signal circuit parameter Cgs while gate contour affects Cgd. The breakdown voltage has strong dependence on gate contour and little dependence on gate length.

Kink phenomena in InAlAs/InGaAs HEMTs are investigated using a two-dimensional (2-D) device simulation that takes into account impact ionization, including nonlocal field effects, and the surface states in a side-etched region at the gate periphery. The simulation model enables us to represent the kink, and it is found that the accumulation of holes generated by the impact ionization has the channel electron density in the side-etched region increase at the bias point where kink appears. When the electron density in the side-etched region is small, the hole accumulation causes a significant increase in that electron density, resulting in a large kink. The simulation results suggest a model in which the kink is described in terms of the modification of the parasitic source resistance induced by the hole accumulation. This model implies a way to eliminate the kink, that is, keeping the electron density in the side-etched region high.

Gallium nitride (GaN) based vertical high electron mobility transistor (HEMT) is very crucial for high power applications. Combination of advantageous material properties of GaN for high speed applications and novel vertical structure makes this device very beneficial for high power application. To improve the device performance especially in high drain bias condition, a novel GaN based vertical HEMT with silicon dioxide $$(\hbox {SiO}_{2})$$(SiO2) current blocking layer (CBL) was reported recently. In this paper, effects of the thickness of CBL layer and the aperture length on the electrical and breakdown characteristics of GaN vertical HEMTs with $$\hbox {SiO}_{2}$$SiO2 CBL are simulated by using two-dimensional quantum-mechanically corrected device simulation. Intensive numerical study on the device enables us to optimize and conclude that devices with $$0.5\hbox {-}\upmu \hbox {m}$$0.5-μm-thick $$\hbox {SiO}_{2}$$SiO2 layer and $$1\hbox {-}\upmu \hbox {m}$$1-μm-long aperture will be beneficial considerations to improve the device performance. Notably, using the multiple apertures can effectively reduce the on-state conducting resistance of the device. On increasing the number of apertures, the drain current is increased but the breakdown voltage is decreased. Therefore, device with four apertures is taken as an optimized result. The maximum drain current of 84 mA at $$\hbox {V}_\mathrm{G}= 1\,\hbox {V}$$VG=1V and $$\hbox {V}_\mathrm{D}= 30\,\hbox {V}$$VD=30V, and the breakdown voltage of 480 V have been achieved for the optimized device.

In this Letter, a novel vertical bipolar junction transistor (BJT) triggered silicon‐controlled rectifier (VBTSCR) is proposed for advanced nanoscale electrostatic discharge (ESD) protection applications. With the help of a vertical NPN transistor in floating base configuration, the new silicon‐controlled rectifier (SCR) structure achieves lower trigger voltage and better clamping capacity than the prior enhanced modified lateral SCR (EMLSCR) under the same layout footprint. The ESD characteristics are measured using the transmission line pulsing tester. Compared with that of EMLSCR, the trigger voltage of VBTSCR drops by 1 V, and the effective ESD robustness of VBTSCR has been doubled significantly. Based on these advantages, the proposed VBTSCR can provide ESD protection for the advanced 1.8/2.5 V input/output circuits more efficiently.

To improve the value of β of a pnp-merged vertical bipolar transistor (VBT) in ‘pseudo-BiCMOS’ technology, a novel VBT design with an inversion layer-extended emitter is proposed. A high emitter injection efficiency of the forward-biased inversion layer is demonstrated in a pnp VBT fabricated in 1 µm compensated CMOS technology.

In order to analyze short-channel effects of MOS transistor ac characteristics, a two-dimensional device simulator has been used to extract MOS transistor capacitances. The results of simulation and measurements agree well. The causes of short-channel effects have been understood and explained by the simulations. Two-dimensional effects and velocity saturation are the main causes of short-channel effects in MOS transistor capacitances. Two-dimensional simulation was found to be a useful tool for studying mobility models, as well as for obtaining capacitance models for circuit simulation.

The performance of bipolar devices (NPN-transistors, lateral PNP-transistors and IIL-gates) in a low-power UHF-process at varying epilayer doping concentration is discussed on the basis of both two-dimensional device simulation and experimental data. While IIL-gates and lateral PNP-transistors would benefit by an increased doping, the observed strong decrease of the NPNs' forward Early Voltage Veaf inmposes a severe restriction on a choice towards raised doping concentrations, since Veaf is an important electrical device parameter in linear analog bipolar processes. The presented results help to find a reasonable, application orientated trade-off between the various electrical device parameters.

High gain p- n- p gated lateral bipolar action in a fully depleted counter-type channel p-MOSFET structure

Design curves of breakdown voltage at field plate edge and effect of interface charge

The major challenge the radio frequency laterally double-diffused metal oxide semiconductor (RF LDMOS) faces today is the linearity and switching delay. In this paper, we propose a new, gate-engineered silicon-on-insulator (SOI) LDMOS device to overcome this problem. The proposed device has three gates arranged in a stepped manner, from the channel to drift region. The first gate uses p+ poly (near the source), whereas the other two gates have n+ poly. The first gate with a thin gate oxide achieves good control over the channel charge. The third gate with a thick gate oxide at the drift region achieves reduced gate to drain capacitance. The arrangement of second and third gates in a stepped manner in the drift region spreads the electric field uniformly. Using two-dimensional device simulations, the proposed LDMOS is compared with the conventional LDMOS. We demonstrate that the proposed device exhibits significant enhancements in linearity, switching delay, breakdown voltage, on-resistance, peak transconductance and gate-drain charge making it highly suitable for RF power amplifiers.

Molecular beam epitaxial growth of high performance In 0.48Ga 0.52P/In 0.20Ga 0.80As/GaAs p-HEMTs using a valved phosphorus cracker cell

A two-dimensional numerical device simulator has been developed specially for the recessed gate 4H silicon carbide(4H-SiC) metal–semiconductor field-effect-transistor (MESFET). By combining numerical techniques, material physics, and measured device characteristics, we are able to use the simulator to extract more information about the new material 4H-SiC, including the mobility, velocity-field curves, and the Schottky barrier height. We have also enabled and used the new simulator to investigate breakdown voltage and thus predict operation limitations of the 4H-SiC device. Simulations indicate that impact ionization is relatively small in 4H-SiC, thereby leading to a very high breakdown voltage of 125 V in a 0.7 μm gate MESFET.

The features of modern complementary bipolar technologies (CB-technologies) for analog applications have been analyzed and the main trends in their development are considered. Different industrial CBtechnologies are compared on the basis of two parameters of complementarity, namely the quality factor (βV A ) and Johnson’s parameter (BV CEO f T ). The p-epitaxial-planar CB-technology has been studied by the method of two-dimensional numerical simulation using the TCAD Sentaurus software for vertical n–p–n and p–n–p transistors. A careful calibration of the parameters of technological and electrophysical 2D models on the basis of test structures has shown sufficient accuracy of the used methodology for practice.