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High-gain emitter inversion layer PNP vertical bipolartransistor in compensated CMOS technology

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Abstract

To improve the value of β of a pnp-merged vertical bipolar transistor (VBT) in ‘pseudo-BiCMOS’ technology, a novel VBT design with an inversion layer-extended emitter is proposed. A high emitter injection efficiency of the forward-biased inversion layer is demonstrated in a pnp VBT fabricated in 1 µm compensated CMOS technology.

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