Wideband VHF and UHF RF Front-End Receiver for DVB-H Application

In this letter, a microwave rectifier array using an automatic input power distribution technique (AIPDT) is proposed to achieve high conversion efficiency over a wide dynamic input power range. The rectifier array employs two rectifier cells operating at low- and high-power levels, respectively, and utilizes AIPDT to distribute the RF input power between them according to the input power level. In this way, a high RF-dc power conversion efficiency (PCE) and a low reflection coefficient over a wide input power range are achieved. For validation, the proposed rectifier array at 2.4 GHz was designed, fabricated, and characterized. The experimental results show that the PCE maintains over 50% when the input power ranges from 2.2 to 26.5 dBm, and the input power range for PCE >30% is from −7 to 30 dBm. Besides, the reflection coefficient remains less than −10 dB over a 40-dB dynamic range (−10 to 30 dBm).

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

In this work, the low power receiver front-end is investigated in the 865-867 MHz unlicensed band. The low noise amplifier (LNA), Mixer, local oscillator and active filter are integrated to investigate the overall performance of receiver front-end. The individual components are studied to optimize the power consumption without degrading the overall performance of receiver frontend. From the results it can be seen that for optimal power of 18mW, 2.01 dB of noise figure was attained. For integrated LNA with mixer, at optimal 48mW power, noise figure was found to be 2.84 dB. The balun circuit in the receiver was replaced by a current amplifier and performance was compared. Receiver front-end for 865-867 MHz at 60mW power with 3.3dB noise figure was obtained.

A 0.2–2.5 GHz active resistive negative feedback low noise amplifier (LNA), based on current-reuse transconductance boosting technique is designed in 0.18-µm CMOS technology. The LNA has the characteristics of high gain, low noise and reasonable power consumption. Meanwhile, the input resistance feedback technology is adopted to greatly increase the matching bandwidth of the input. Post-layout simulated results get a 3-dB bandwidth of 0.2–2.5 GHz and 19.2 dB power gain. Its input/output matching is less than −10 dB in the 0.1–4.5 GHz frequency range, and the input third-order intercept point (IIP3) is greater than −9 dBm. The LNA noise figure (NF) is 2.5–3.16 dB in the 0.2–2.5 GHz. The circuit consumes 24 mW DC power from a 3 V supply and the layout size is 980 µm × 530 µm.

This paper discusses the design of the narrow band cascode source degeneration Low Noise Amplifier (LNA) operational at 5 GHz frequency. The LNA was designed with standard gpdk 180 nm technology using Cadence Virtuoso tool. In this paper, source degenerated inductor with cascode and current mirror configuration have been used. For the design of input and output matching circuits, π-match and L-match have been used respectively. Performance parameters like noise factor, S-parameters, gain, linearity etc. have been analysed for the proposed design. Various kinds of analysis like sp analysis, noise analysis, dc analysis, ac analysis and harmonic analysis have been performed for the validation of design. Analog Mixed Signal (AMS) CMOS process is utilized for the design of 5 GHz LNA. This LNA achieves source degeneration inductance feedback which is useful for low noise factor for 5GHz wireless applications.

This paper presents a new design of inductorless wideband front-end receiver using 130 nm CMOS technology for LTE bands of 0.7 GHz to 3 GHz. The RF front-end receiver consists of the microstrip antenna, self-bias resistive feedback low-noise amplifier, active balun and folded mixer architecture. The miniature antenna provides good matching results for the entire band of interest. Optimization of low-noise amplifier using linearization technique followed by NMOS switches mixer stage are effectively used to achieve maximum gain, low noise figure, and low power consumption. The designed receiver exhibits a maximum gain of 22 dB, maximum noise figure of 7.5 dB, minimum 3rd order intercept point (IIP3) of −9.2 dBm, and DC power consumption of 22 mW at 1.2 V power supply. Using these optimizations, our proposed receiver can be a good candidate for LTE applications.

The wideband receiver front end composed of a low noise amplifier (LNA) and a bypass path is presented. A conventional current reused LNA with an inductor as a radio frequency (RF) choke is presented to provide reused DC current path. In this brief, the proposed LNA adopts the inductorless circuit topology and the current reused technique to realize compact size, stability condition and bandwidth extension. This receiver front end is fabricated in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.15~{\mu }{\mathrm {m}}$ </tex-math></inline-formula> depletion mode pHEMT technology. The frequency band of the receiver front end is 5-10 GHz, and the chip area is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.6\,\,{\times }\,\,0.5\,\,{{\mathrm {mm}}}^{2}$ </tex-math></inline-formula> . Measured results show that the LNA gain is 21.4-11.5 dB and noise figure (NF) is less than 2.7 dB over 5-10 GHz with 34.3 mW power consumption. For the bypass path, the insertion loss is 1.8-3 dB, and the input and output return loss are better than 10 dB within 5-10 GHz.

In this work the low-IF receiver for 60 GHz wireless system is presented using 40nm CMOS technology. The individual blocks of receiver front-end includes 3-stage low noise amplifier (LNA), mixer, low pass filter (LPF). These blocks are optimized for low power while maintaining other performance metrics. The Radio Frequency (RF) receiver front-end with 3stage single-ended LNA and differential LNA were designed and compared. The incorporation of current amplifier improves the overall performance of receiver. It was observed that RF frontend receiver with single-ended LNA offers 31.11 dB conversion gain (CG) and 3.35 dB noise Figure (NF) whereas receiver with differential LNA offers 41.13 dB CG and 2.63 dB NF. From the results it can be seen that the performance of differential LNA receiver is better than single ended LNA receiver. The details of the design suggest that receiver with differential LNA can be a potential candidate for the transceiver applications.

Microwave integrated systems in silicon provide a low cost, low power and high yield solution for wideband data communication, radar, and many other applications. Phased-array systems are capable of steering the radiation beam by electronic means, emulating the behavior of a directional antenna. This dissertation is dedicated to presenting various techniques to implement microwave integrated phased-array receivers in silicon-based technologies in the context of three design examples. A 24-GHz 0.18-µm complementary metal oxide semiconductor (CMOS) front-end was demonstrated. The front-end consists of a low noise amplifier (LNA) and a mixer. The LNA utilizes a novel topology common-gate with resistive feedthrough to obtain low-noise performance. The entire front-end achieves a 7.7dB noise figure and a 27.5dB power gain. A fully integrated 8-element 24-GHz silicon germanium (SiGe) phased array receiver was implemented. The receiver uses two-step downconversion and local oscillator (LO) phase shifting with 4-bit resolution. The signal is combined at the 4.8-GHz intermediate frequency. The 16 phases of 19.2-GHz LO signal are generated with a voltage controlled oscillator (VCO) and symmetrically distributed to the phase selectors at all path. Appropriate phase sequence is applied to the phase distribution transmission lines to minimize mismatch. An integrated frequency synthesizer locks the 19.2-GHz VCO output to a 75-MHz external reference. Measured array patterns show a peak-to-null ratio of more than 20dB and a beam steering range covering all signal incident angles. An integrated 4-element 77-GHz SiGe wideband phased-array transceiver was implemented. Two-step conversion is used at both the receiver and the transmitter. A differential phase of 52 GHz is generated by the VCO and distributed to all RF paths at the transmitter and receiver. The phase shifting is performed at the LO ports of the RF mixers using continuous analog phase shifters. The quadrature signal of the second LO frequency is generated by dividing the VCO frequency by a factor of 2 using a cross-coupled injection-locked frequency divider. The signal combining is performed at IF with an active combining amplifier. The receiver achieves a 41dB gain at 80 GHz with 3 GHz of bandwidth. The 52-GHz-to-50MHz frequency divider chain obtains 7% locking range.

High-performance low dropout regulator (LDO) chips are core components that provide clean power for high-precision sensors, radio frequency (RF) circuits, low noise amplifiers and other noise-sensitive circuits. In the reported literature, the designed LDO chip has advantages in certain parameters, but it cannot meet all the requirements of a high power supply rejection ratio (PSRR), low output noise and low standby current at the same time, which makes the high-end applications of LDOs greatly limited. In this paper, an LDO chip with high PSRR, low output noise and low standby current has been designed and fabricated. By increasing the loop gain, introducing an improved feedforward path, and adopting isolated power supply, the PSRR of the LDO at different frequency bands is greatly improved. By optimizing the design of the error amplifier (EA) and adding a low-pass filter to filter out the reference noise, the output voltage noise of the LDO is reduced. Within the depletion process and an optimized reference structure, the standby power consumption of the LDO is reduced without damaging the output voltage accuracy. The chip is taped out with SMIC’s 0.18 μm/5 V/BCD process. The measured PSRR of the chip is as high as 95dB at a frequency of 1 kHz, and the high-frequency (1 MHz) PSRR is above 45 dB. The amplitude of integrated output noise is below 5.4 μVrms within the frequency range of 10 Hz to 100 KHz. When the load current is zero, the measured standby current is less than 400 nA. The test results indicate that the chip has excellent performance in terms of PSRR, output noise and standby power consumption.

In this paper, a Multi-Band Ku-band down converter was designed for reception of multi-band digital satellite broadcasting. The Multi-band low-nose down converter was designed to form four local oscillator frequencies (9.75, 10, 10.75 and 11.3GHz) representing a low phase noise due to VCO-PLL with respect to input signals of 10.7 to 12.75GHz and 3-stage low noise amplifier circuit by broadband noise matching, and to select an one band of intermediate frequency (IF) channels by digital control. The developed low-noise downconverter exhibited the full conversion gain of 64dB, and the noise figure of low-noise amplifier was 0.7dB, the P1dB of output signal 15dBm, and the phase noise -73dBc@100Hz at the band 1 carrier frequency of 9.75GHz. The low noise block downconverter (LNB) for receiving four-band digital satellite broadcasting designed in this paper can be used for satellite broadcasting of vessels navigating international waters.

We propose and experimentally demonstrate a photonic millimeter-wave frequency divider based on a super-harmonic injection-locked optoelectronic oscillator (OEO) and an optical frequency comb. The optical frequency comb generator is incorporated into an OEO loop to create broadband comb lines with low noise. By injecting a millimeter-wave with frequency around N times of the fundamental oscillating frequency f0 of the OEO, the injection signal can be down-converted to an intermediate frequency (IF) signal close to the oscillating frequency of the OEO. The free running OEO is synchronized with the IF signal via an injection locking mechanism. Consequently, it forms an injection-locked frequency divider as the frequency ratio between the injection signal and OEO's output signal is precisely equal to N. We carry out an experiment to divide the 45 GHz signal into 7.5 GHz and the experimental results agree well with the theoretical analysis. By changing the frequency of the injection signal, division ratio from 2 to 5 is also demonstrated on one setup. Due to the broadband spectra of the optical comb and low phase noise characteristics of the OEO, it is potential to realize very large division ratio and low phase noise for multiple input frequencies mf 0 .

In this paper, a wideband CMOS radio frequency (RF) front-end for digital video broadcasting-handheld (DVB-H) receiver is proposed. The RF front-end circuit is composed of a single-ended resistive feedback low noise amplifier (LNA), a single-to-differential amplifier, an I/Q down-conversion mixer with linearized transconductors employing third order intermodulation distortion cancellation, and a divide-by-two circuit with LO buffers. By employing a third order intermodulation (IMD3) cancellation technique and vertical NPN bipolar junction transistor (BJT) switching pair for an I/Q down-conversion mixer, the proposed RF front-end circuit has high linearity and low low-frequency noise performance. It is fabricated in a 0.18µm deep n-well CMOS technology and draws 12mA from a 1.8V supply voltage. It shows a voltage gain of 31dB, a noise figure (NF) lower than 2.6dB, and an IIP3 of -8dBm from 470MHz to 862MHz.

This paper presents a wideband inductorless Low Noise Amplifier (LNA) using a technique for canceling 2nd and 3rd order intermodulation products at the same time and hence achieving high second and third order Input Intercept Point (IIP2 and IIP3) at RF and microwave frequencies. The LNA also makes use of noise canceling stage to achieve low noise characteristics and low noise figure in the whole bandwidth. The LNA was designed in 90-nm CMOS process and consists of a shunt feedback common-source input stage to provide wideband input impedance matching, followed by a noise canceling stage. The common source input stage employs two transistors in parallel biased at different operating regions which perform distortion cancellation. IIP2 and IIP3 of the designed LNA are +41dBm and +2.4dBm respectively. The LNA achieved the voltage gain of 17dB while having the noise figure below 2dB from 500MHz–5GHz.

Wireless communication continues to lead the world. The term “wireless” significantly influences everything from telephone to satellite communication. Recent years have seen the need for appropriately built Low Noise Amplifiers (LNAs) in receiver front end because of the modem wireless communication in broadcast and microwave radio. In this paper a high performance LNA for the radio frequency range is presented. To achieve high gain a three stage LNA with each stage as Cascode stage is considered here. The simulation shows that the presented LNA has a gain of 26.12 dB and a Noise Figure (NF) of 2.6 dB. The achieved output and input returns losses are -8.4 dB and -11.6 dB respectively.