Strained bipolar charge plasma transistor as a high speed LIF neuron

A self-aligned vertical Bipolar Charge Plasma Transistor (V-BCPT) with a buried metal layer between undoped silicon and buried oxide of the silicon-on-insulator substrate, is reported in this paper. Using two-dimensional device simulation, the electrical performance of the proposed device is evaluated in detail. Our simulation results demonstrate that the V-BCPT not only has very high current gain but also exhibits high BVCEO · fT product making it highly suitable for mixed signal high speed circuits. The proposed device structure is also suitable for realizing doping-less bipolar charge plasma transistor using compound semiconductors such as GaAs, SiC with low thermal budgets. The device is also immune to non-ideal current crowding effects cropping up at high current densities.

Two-zone SiGe base heterojunction bipolar charge plasma transistor for next generation analog and RF applications

In this paper, we have proposed a new device structure of schottky-collector bipolar charge plasma transistor (SC-BCPT) with an extended base of thickness (t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> = 25 nm). The charge plasma concept eliminates different doping requirements for emitter and base regions, as a result, simplified fabrication process and improved current gain (ß). However, extended base concept yields improved cut-off frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of the proposed device. The Hafnium and stack of TiN/HfSiOx/SOI doped with Fluorine metal electrodes were employed to induce electrons and holes concentration at the emitter and base regions, respectively. Two-dimensional TCAD simulations of the proposed device demonstrate higher current gain of 37×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> and a peak cut-off frequency of 43.04 GHz as compared to the conventional SC-BCPT.

This paper presents HIBTRA (High Speed Bipolar Transistor Analysis), a high speed non-linear bipolar transistor circuit simulation package. The paper discusses about the modelling of Bipolar Junction Transistor operated at high speed in the sinusoidal small signal and the transient region of operations. The package uses a high frequency model non-linear circuit elements for accurate analysis. The package also uses transistor's lumped circuit model to calculate devices electrical parameters, and it also does dynamic simulation. It also includes the conventional model as a special case. Model verification has also been done by simulation.

Reducing the size of silicon devices is accompanied by an increase in the effective rate of electrons, decrease transit time and the transition to a ballistic work.Power consumption is reduced too. Formation of large integrated circuits structures onSi-homotransition reduces their frequency range and performance.Nowadaysproposed several new types of devices and technologies forming of large integrated circuits structures that based on high speeds and mobility of electrons in GaAs, and small size structures.These include, for example, the heterostructure field-effect transistors on a segmented doping, bipolar transistors with wide-emitter, transistor with soulful base, vertical ballistic transistors, devices with flat-doped barriers and hot electron transistors as element base of modern high-speed large integrated circuits.In this article we consider graded-gap technology formatting as bipolar and field-effect transistors, which are the basis of modern high-speedof large integrated circuits structures.

Around 1970 Intel discovered it could put 2,000 transistorsor perhaps a few moreon a single NMOS chip. In retrospect, this may be said to mark the beginning of very large-scale integration (VLSI), ...

In this review paper, the evolution of the microelectronic bipolar transistor is tracked. Since its invention in 1947, the BJT has undergone vital enhancement of its electrical performance thanks to intensive research efforts through the years. The main task was to increase the speed of the transistor while keeping its current gain high enough for satisfactory circuit performance. This has been achieved by transistor scaling. The lateral dimensions shrunk thanks to the advancement in lithography and new isolation techniques, especially trench isolation, as well as development of self-aligned structures. The vertical dimensions shrunk by the introduction of controllable doping technologies such as ion implantation and low temperature epitaxy. Further scaling could be possible by using SiGe-based and AlGaAs/GaAs HBTs. Bipolar transistors with an f/sub T/ of greater than 140 GHz are routinely fabricated now. Especially GaAs HBTs can be further scaled to achieve more speed. These high speed transistors are required for main-frame computers and modem communication circuits.

Charge plasma based devices are gaining interest due to various reasons, since these devices doesn’t require conventional ways of creating different doping regions, therefore these devices are free from various doping related issues related, as random doping fluctuations, doping activations and the requirement of high temperature annealing are absent in these devices. In this work we put forward a novel lateral pnp bipolar transistor on silicon on insulator. Metals of different work function are used to induce n and p type charge plasma on undoped silicon to have emitter, base and collector regions. The 2D simulation study has revealed that a very high current gain is achieved in the proposed device in comparison to conventional pnp transistor. The charge plasma concept is very much appropriate in surmounting the doping related issues such as diffusion or ion implantation, random doping fluctuations and high thermal budget in current nano devices.

Chapter 2 - Power Semiconductors

Recovery and stress dynamics in bipolar transistors and MOS devices

The performance of high speed digital integrated circuits, defined here as those requiring operation at high clock frequency, is generally more sensitive to material properties and process techniques than ICs used at lower frequencies. Obtaining high speed and low power concurrently is especially challenging. Circuit architectures must be selected for the device and application appropriately. This paper presents simple models for high speed digital IC performance and applies these to the FET and bipolar transistor. Heterojunction devices are compared with those using single or binary materials. Circuits for high speed SSI and low power VLSI applications are described, and their performance is surveyed.

A new structure for a symmetric bipolar charge-plasma transistor device with an extruded base is proposed. The charge plasma and extruded base concepts are used to increase the current gain and cutoff frequency of the proposed device, respectively. Metal contact hafnium accumulates electrons in the emitter/collector (E/C) regions and platinum accumulates holes in the base region. Using the metal contact of different work functions, the electrons and holes are accumulated in a lightly doped silicon film to create the E/C and the base regions, respectively. Two-dimensional simulations of the proposed device demonstrate that it has a higher current gain of 9 × 106 and a peak cutoff frequency (fT) of 87.3 GHz. Furthermore, the fT for different silicon film thicknesses and base widths is optimised.

Search for high speed has over the years focussed on miniturization and high performance semiconducting materials. Scaling up in speed reaches a saturation as the dimensions are reduced because parasitics do not entirely scale down, particularly in integrated circuits. As a result new material systems e.g. GaAs/AlGaAs modulation doped structures with enhanced transport properties have received a great deal of attention. The propagation delay in Si devices (both bipolars and FETs) appear to have reached a limit at around 30 ps while the bulk GaAs FETs operate around 15 ps. Near 10 ps and sub 10 ps switching speeds however belong to modulation doped GaAs/AlGaAs FETs with ~ 0.5μ gate lengths. Hetero junction GaAs/AlGaAs bipolar transistors are expected to reach the 10ps range in a few years being at ~30 ps at the present time. It is becoming very clear that the progress below 10 ps in a given material system is very difficult because of parasitics. The 10 ps switchings time obtained for an individual device (gate) can not be maintained in a real circuit where a chain of gates are used, again because of parasitics and interconnects causing delays. If it were not for the delays associated with the input capacitance changing time and other parasitic effects, intrinsic delays of about 1 ps should be possible. In field effect transistors for example, it is fair to assume that a great portion of the delay arises from input and output charging times. Obviously lowering the lateral dimension (e.g. gate) alone does not necessarily lead to expected improvements in speed. This is even more so in heterojunction bipolar transistors where the input charging time accounts for about 75% of the total delay time: therefore, reducing the base width further, well under 0.1μm may not necessarily lead to faster operation.

A composite collector heterostructure InGaAs/InP bipolar transistor (CCHBT) is described. The collector design assures both the high breakdown voltage, BV/sub CEO/, and the high speed needed for practical IC applications. The microwave performance of the CCHBT is presented. The authors have fabricated and tested monolithic transimpedance amplifiers based on these composite collector transistors. A bandwidth of 28 GHz and a gain of 40 dB Omega were obtained.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 1.6 GHz fully monolithic silicon bipolar LC current-controlled oscillator (CCO) circuit implemented in a 0.8 µm BiCMOS technology and characterized for use in wireless applications is presented. The integrated resonator circuit uses high speed (18 GHz) bipolar transistors, a 14 nH rectangular spiral inductor fabricated by using a standard 2-level metallization, and a wideband pn-varactor structure. Additionally, to save chip area, the integrated capacitors were fabricated below the planar inductor structure. In order to aid the IC design, a simple equivalent circuit model for the integrated inductor on silicon was developed and tested. The measured quiescent power dissipation of the integrated CCO circuit is 1.9 mW to 5.5 mW from a supply of 2–3 V, and a typical phase noise varies from −82 to −86 dBc/Hz at 100 kHz offset.