A Novel High Performance Boost Power Factor Correction (PFC) Converter with an improved Zero Voltage Transition (ZVT) technique

Dynamic response of boost power factor correction (PFC) converter operating in continuous-conduction mode (CCM) is heavily influenced by low-bandwidth of voltage control loop. A novel tri-state boost PFC converter operating in pseudo-continuous-conduction mode (PCCM) is proposed in this paper. An additional degree of control-freedom introduced by a freewheeling switching control interval helps to achieve PFC control. A simple and fast voltage control loop can be used to maintain a constant output voltage. Furthermore, compared with boost PFC converter operating in conventional discontinuous-conduction mode (DCM), boost PFC converter operating in PCCM demonstrates greatly improved current handling capability with reduced current and voltage ripples. Analytical and simulation results of the tri-state boost PFC converter have been presented and compared with those of the boost PFC converter operating in conventional CCM and DCM. Simulation results show excellent dynamic performance of the tri-state boost PFC converter.

Power Factor Correction (PFC) converter is a key component in modern switching power supplies, while high efficiency and high power density are the main goals of PFC converter. In this paper, taking a single-phase Boost circuit as an example, a PFC converter with 300 kHz switching frequency and 1 kW output power which is based on continuous inductor current (CCM) mode is designed to reduce the volume of the core component and improve the power density of the converter. The paper includes the detailed design of the boost inductor, the analysis of the loss of the inductor at high frequency operation and the loss of the PFC converter. Finite element analysis is used to verify that the winding loss can be reduced by taking multi-strand wire winding. New semiconductor devices CoolMOS and SiC are employed which can reduce the loss effectively. The experimental results are provided which demonstrate that the employ of SiC diode and multi-strand wire winding can enable enhanced performance on efficiency.

The operation of the two-phase interleaved CRM Boost power factor correction (PFC) converter with coupled inductors is analyzed in this paper. Since the equivalent inductance varies with the switching mode and duty cycle, the current mode control method should be adopted to achieve PFC rather than the voltage mode control. The switching frequency is derived, and the self inductance is discussed in term of the minimum switching frequency, which should be higher than 20 kHz to avoid acoustic noise. The design methodology of the coupled inductors is presented as well. Compared to the discrete inductors, the coupled inductor has small size and low copper usage, so the power density of the PFC converter can be increased.

In this paper, an improved Zero-Voltage-Transition (ZVT) two-cell interleaved boost Power Factor Correction (PFC) converter is proposed and investigated. A new auxiliary circuit is designed and added to two-cell interleaved boost converter to reduce the switching losses. Only one auxiliary switch is used in the active soft switching auxiliary circuit. The main advantage of this auxiliary circuit is that it not only provides ZVT in the boost switches but also provides soft switching in the auxiliary switch and passive diodes. Therefore, the switching losses of the converter can be reduced. Compared to the previous published soft switching interleaved boost converters, only one auxiliary switch is needed in the auxiliary unit, so the auxiliary unit and control circuit are simple. A 1kW, 50 kHz two-cell interleaved boost PFC converter with an improved ZVT auxiliary circuit has been simulated using average current control method and the results are presented. Simulation results show that the main switches, the auxiliary switch and passive diodes are operating under soft switching mode.

The use of power factor correction (PFC) converters is widely discussed and considered for most off-line power supplies. For low power applications, boost PFC converters operated in discontinuous conduction mode (DCM) or boundary conduction mode (BCM) mode are usually employed. The main advantage of BCM mode is the reduction of reversal recovery loss of diode and simple control, especially at the high-line light-load condition. In this paper, a digital-controlled method for boost PFC operating under boundary conduction mode without input voltage sensing is proposed. The digital PI controller voltage is used to determine the constant on-time period and the comparator block inside the DSP controller is employed to detect the zero-crossing of inductor current for turning on the main switch. Therefore, the size and cost are reduced significantly. A 200W boost PFC prototype is implemented and tested to verify the feasibility of the proposed control scheme.

This manuscript deals about the configuration of a power factor correction (PFC) converter feeding a drive of brushless DC (BLDC) motor for medium and low power equipment. The front-end PFC converter working in discontinuous inductor current mode (DICM) is applied for regulating the DC link voltage and PFC is achieved inherently. The BLDC motor speed is adjusted by regulating the DC link voltage of voltage source inverter (VSI) feeding to motor. The DC link voltage of drive system is maintained by a single DC voltage actuator. A prototype is developed for evaluating the performances of anticipated drive for the speed control over a broad range. The performance of anticipated drive is also validated for its function at varying AC mains voltages (90V–265V). Test results for power quality (PQ) parameters are compared with restrictions of power quality standard IEC 61000-3-2.

In order to further increase the power density of power factor correction (PFC) converter, a structure of passive integration is proposed by combining EMI filter and Boost inductor in one magnetic component for PFC converters in this paper.

The switching frequency of the boost power factor correction (PFC) converter operating in critical conduction mode (CRM) varies in a line cycle, making the conducted electromagnetic interference (EMI) spectra of the converter appear great differences under different input voltage and load conditions. The EMI filter should be designed according to the worst conducted EMI spectrum of the converter, so as to suppress the conducted EMI of the converter to be lower than the standard limits under all working conditions. This paper analyzes the characteristics of the common-mode (CM) and differential-mode (DM) noise spectra of the CRM boost PFC converter, and discusses the effects of the varied switching frequency on the peak, quasi-peak (PK), and average (AV) conducted EMI spectra. It is revealed that, for the conducted EMI limits defined in EN55022 class B, which are specified within 150 kHz to 30 MHz, the EMI filters required for suppressing the QP spectra of the conducted EMI of the CRM boost PFC converter are larger than that for suppressing the AV spectra, and the QP values of the conducted EMI under all working conditions are lower than a certain maximum boundary. The input voltage and load conditions for the worst CM and DM noise spectra of the converter are derived in this paper, thus the repetitive measurements and numerical calculations are avoided. A CRM boost PFC converter prototype is fabricated, and the evaluation of the measured conducted EMI spectra and the EMI filter design example verified the theoretical analysis.

In this paper, a series-capacitor-based interleaving buck power factor correction (PFC) converter is proposed, the intermediate energy storage capacitance of which is operated at discontinuous capacitor voltage mode (DCVM), and automatic power factor (PF) correction for this converter is obtained. Moreover, the voltage across the series capacitor of the proposed PFC converter is clamped at the input voltage, and thus peak voltage stress existed in the traditional DCVM buck PFC could be relieved. By effectively regulating the charge/discharge time for the series capacitor, ultrahigh step-down conversion ratio of the proposed converter is achieved, the conversion ratio of which is independent of the duty cycle and only related to the switching frequency and circuit parameters. Therefore, high PF can be obtained due to very narrow deadtime of the input current. Meanwhile, the proposed PFC converter can realize the soft turn- on of part power switch and soft turn- off of part power diodes. In addition, comparing with the traditional discontinuous inductor current mode PFC, the input current of the proposed PFC converter is continuous so that the peak value and root-mean-square value of input current can be reduced. The operational principle, performance analysis, and parameter design principle are given in this paper. The analysis results show that the PF and total harmonic distortion are also independent of the duty cycle. Finally, a 220-Vac input, 60 W/15 V output experimental prototype is built to verify the validity of the theoretical analysis.

In this study, an extended idea has been introduced to improve the dynamic response of single-phase active power factor correction (PFC) converter. A highly non-linear DC-DC converter with inherent parameter uncertainties and the harmful effects due to large disturbance in line voltage are tackled by proposed two sided latched pulse-width-modulation technique with sophisticated feedback system. The effort is made to achieve improvement in the dynamic response of active PFC converter with the primary objective of achieving nearly unity input power factor. The dynamic performance of the proposed converter is analyzed in Power Sim (PSIM) package and is exactly verified with 400 V, 500 W, and 100 kHz laboratory prototype for step change in input voltage and load current.

In low power single-phase power supplies, single-stage AC/DC converters allow meeting low frequency harmonic regulations such as EN 61000-3-2 and they result a cheaper and simpler solution than the two stages approach. The series inductance interval (SII) gives its name to a new family of single-stage power factor correction (PFC) converters which have been developed to obtain three features: a storage capacitor voltage below the peak value of line voltage, low variation of this voltage with line and load changes, and input current harmonics lower than the EN 61000-3-2 Class D limits for the full load power range. This paper present the principle of operation of the SII converters besides the first experimental results.

In low‐voltage distribution systems, the increased penetration of power electronic devices leads to the decentralization of harmonic sources, which puts the sensitive loads or communication systems in the risk status. The conventional methods of point‐to‐point harmonic control are not applicable. In order to solve this problem without increasing additional investments, this paper focuses on mitigating the harmonic interference through the power factor correction (PFC) converter. Hence, a critical conduction mode (CRM) single‐phase boost PFC converter with adaptive harmonic compensation (AHC) control is proposed to reduce the harmonic interference at user side. Firstly, the feed‐forward control loop of a PFC converter is decoupled into the fundamental branch and harmonic branch to trace the harmonic interference and generate the compensation current. Then the compensation gain is designed by the compensation loop gain and compensation capacity of PFC converter. Meanwhile, the characteristics of the PFC converter are analyzed to study the effect of the AHC control on the active power transmission and output load, which can provide important support for the proposed method in application. Finally, a 160‐W experimental prototype is built to verify the effectiveness of the proposed AHC control.

In this paper, a modified power factor correction (PFC) converter based on Sheppard-Taylor PFC converter is proposed, and operation principle of this converter is studied. Compared with conventional Sheppard-Taylor converter, the proposed converter has many advantages such as less ripple of input current that can considerably improve Sheppard-Taylor converter operation. Then sliding mode control is applied to proposed converter and obtained results are studied.

Digital control of a boost power factor correction (PFC) converter requires sampling of the input current. As the input current contains a considerable amount of switching ripple and high frequency switching noise, the choice of the sampling instant is very important. To avoid aliasing without employing a (very) high sampling frequency, the sampling is synchronized with the pulse width modulation (PWM). Sampling algorithms employing this technique successfully reject the input current ripple but are not immune to the high frequency switching noise present on all sampled signals. Therefore, a new sampling algorithm, intended for center-based or symmetric PWM, is deduced with as most important features: switching noise immunity, straightforwardness, accurate measurement of the averaged input current and the need for only few processor cycles. The operating principle, design issues and a theoretical study of the input current error induced by the sampling algorithm due to sampling instant timing errors are derived. All theoretical results are validated experimentally by using a digitally controlled boost PFC converter switching at 50 kHz.

Buck-buck/Boost power factor correction (PFC) converter is a great choice to compensate the inherent dead zones in the input current of buck PFC converter. However, whether the converter operates with traditional constant on-time control in critical conduction mode (CRM) or with conventional constant duty-cycle control in discontinuous conduction mode (DCM), the power factor (PF) is low, especially at low input voltage. Therefore, fixed on-time ratio control (FOTRC) and fixed duty-cycle ratio control (FDCRC) are proposed for CRM/DCM buck-buck/boost PFC converter to achieve high PF, respectively. Both control methods maximize PF over wide input voltage range by adjusting on-time or duty-cycle of buck/boost mode and buck mode. Compared with the traditional controls, the proposed control methods also have advantage of increasing efficiency. Furthermore, for improving dynamic response performance, smooth and rapid dynamic response control (SRDRC) is put forward, which can reduce the regulation time and output voltage overshoot/undershoot when the load or input voltage changes abruptly. In addition, the implementation circuits combining FOTRC/FDCRC and SRDRC are designed. Two prototypes have been built and tested in the lab to demonstrate the validity of the theoretical analysis.